Marvell International Limited

Vinay Bhat Soori

Sreenivasula Reddy Dhani Reddy

Md Nadeem Iqbal

Disclosed is a multi-port memory array configured to minimize resistance-capacitance (RC) delay caused by wordline coupling. In each row of the array, a first voltage boost circuit is connected to the distal ends of a first wordline and a second wordline and boosts a first voltage on the first wordline during an access period when the first voltage is transitioning from low to high and when, concurrently, a second voltage on the second wordline is either low or transitioning to low. Optionally, a second voltage boost circuit is also connected to the distal ends of the first and second wordlines and boosts the second voltage on the second wordline during a different access period when the second voltage is transitioning from low to high and when, concurrently, the first voltage on the first wordline is either at low or transitioning from high to low. Also disclosed is a corresponding method.

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Karnataka, India

Vinay Bhat Soori