Intel Corporation

Vinay B Chikarmane

Kevin Fischer

Brennan Peterson

Christopher P Auth

Joseph M Steigerwald

Andrew W Yeoh

Jinhong Shin

Valery M Dubin

Chi-Hwa Tsang

Christopher D Thomas

Yang Cao

Daniel J Zierath

Jick M Yu

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.

Stressed barrier plug slot contact structure for transistor performance enhancement

Embodiments of barriers to use in semiconductor devices are presented herein.

Barrier formation and structure to use in semiconductor devices

In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a zincating process, and selectively depositing a sacrificial metal or metal alloy cap on the aluminum gate layer by displacing the zinc layer. This embodiment enables the SAC process flow on devices with Aluminum gates.

Method for manufacturing a semiconductor device using the self aligned contact (SAC) process flow for semiconductor devices with aluminum metal gates

A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.

Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement

Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.

Reducing corrosion in copper damascene processes

A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.

Barrier process/structure for transistor trench contact applications

An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

Modified electroplating solution components in a low-acid electrolyte solution

Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.

Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing

Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.

Seed layer treatment

A method for forming an aluminum or aluminum alloy plug in the fabrication of a semiconductor device. An opening is formed in a wafer. A titanium wetting layer is then deposited over the wafer and lines the sidewalls and bottom of the opening. The opening is then filled with aluminum in two steps, both steps being performed at approximately the same temperature. The first aluminum deposition step is performed at a first (slower) deposition rate. The second aluminum deposition step is performed at the same temperature as the first deposition step but at a different (or second/faster) deposition rate until the opening is completely filled.

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Portland, OR, United States of America

Vinay B Chikarmane