Texas Instruments Corporation

Vinay Agarwal

Joel Martin Halbert

Robert E Seymour

A bus driver circuit (FIG.) is disclosed. The circuit includes a signal lead of a bus () and a reference terminal (Vss). A first transistor (MN) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

Transition rate controlled bus driver circuit with reduced load sensitivity

A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits () each including a high-voltage sampling switch circuit () having a first terminal () coupled to a first terminal of a corresponding capacitor () and a second terminal coupled to receive an analog input signal (V). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (). Each switching circuit () also includes a low-voltage conversion switch circuit () coupled to the intermediate conductor () and a combinational logic circuit () applying low-voltage signals to the conversion switch circuit and a level-shifting circuit () that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal () to the analog input signal and the intermediate conductor.

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Tucson, AZ, United States of America

Vinay Agarwal