Globalfoundries Inc.

Psiquantum Corp.

International Business Machines Corporation

Lam Research Corporation

Globalfoundries U.S. Inc.

Globalfoundaries Inc.

Vimal Kumar Kamineni

Ruilong Xie

Yong Liang

Mark V Raymond

Faraz Najafi

Mark G Thompson

Abner Bello

George Kovall

Balasubramanian Pranatharthiharan

Xunyuan Zhang

Nicholas V Licausi

Robert J Miller

Chengyu Charles Niu

Chia-Ming Chang

Kangguo Cheng

Chanro Park

Praneet Adusumilli

Muthumanickam Sankarapandian

William James Taylor, Jr

Andre P Labonte

Syrus Ziai

Randolph F Knarr

Adra Carr

Derya Deniz

Abhijeet Paul

Vitor Riseti Manfrinato

Chia-Jung Chung

Georges Jacobi

Andrew Mark Greene

Su Chen Fan

Guillaume Bouche

Viraj Yashawant Sardesai

Wenhui Wang

Xuan Lin

Jeremy Austin Wahl

Nigel Graeme Cave

Gabriel J Mendoza

Daniel P Smith

Jason Cantone

Michael Wedlake

Ann Melnichuk

Himani Suhag Kamineni

Maxwell Lippitt

Ali Khakifirooz

Juntao Li

Veeraraghavan S Basker

Hui Zang

Lars W Liebmann

Xiuyu Cai

Oscar Van Der Straten

Min Gyu Sung

Hoon Sik Kim

Daniel Chanemougame

Steven J Bentley

Shesh Mani Pandey

Cornelius Brown Peethala

Raghuveer Reddy Patlolla

James John Kelly

Scott Beasor

Michael Vincent Aquilino

Shariq Siddiqui

Balaji Kannan

Suraj Kumar Patil

Shafaat Ahmed

Wenguang Li

Hari Prasad Amanapu

Katsunori Onishi

Matteo Staffaroni

Eric Dudley

Khanh Tran

James P McMahon

Chih-Chiang Chang

Chang Seo Park

Bala S Haran

Pei Liu

Mark Thompson

Dinesh R Koli

Stan Tsai

Benjamin G Moser

Vishal Chhabra

Neal A Makela

Sugirtha Krishnamurthy

Takashi Orimoto

Luu Nguyen

Himani Kamineni

A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.

Structure and method to remove semiconductor chip material for optical signal access to a photonic chip

An optical interposer can be formed from multiple wafers, including a photonic integrated circuit wafer and an interposer wafer. The photonic integrated circuit wafer can be bonded to a rigid carrier structure, and material near waveguides can be removed such that the waveguides can be coupled to waveguides of the interposer. The photonic integrated circuit can be separated into multiple rigid dies which can be bonded to the interposer separately. Additional processing can be performed to form electrical connections to the rigid dies to form an ultra-low optical interposer.

Low loss optical interposer

A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.

Photonic integrated circuit

A system includes a classical computing system and one or more quantum computing chips coupled to the classical computing system. The one or more quantum computing chips includes one or more electro-optic devices. Each electro-optic device includes a substrate, a waveguide disposed on top of the substrate, and a layer stack disposed on top of the waveguide and including a plurality of electro-optic material layers interleaved with a plurality of interlayers. Each electro-optic device further comprising a waveguide core disposed on top of a portion of the layer stack. The plurality of interlayers are characterized by a first lattice structure and the plurality of electro-optic material layers are under tensile stress and are characterized by a second lattice structure and crystallographic phase.

Engineered electro-optic devices

A superconductor device includes a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen, and a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen, and superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

Superconducting nanowire single photon detector and method of fabrication thereof

An optical device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, a light sensitive component (e.g., a photodetector) in the dielectric layer and coupled to the waveguide, and a plurality of light isolation structures in at least one of the substrate or the dielectric layer and configured to prevent stray light from reaching the light sensitive component. In some embodiments, a light isolation structure in the plurality of light isolation structures includes two opposing sidewalls and a filling material between the two opposing sidewalls. The two opposing sidewalls include an optical isolation layer. The filling material is characterized by a coefficient of thermal expansion (CTE) matching a CTE of at least one of the substrate or the dielectric layer.

Isolation of waveguide-integrated detectors using a back end of line process

An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers and a waveguide core adjacent to the layer stack. The waveguide may include a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.

In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

Barium titanate films having reduced interfacial strain

A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.

Germanium mediated de-oxidation of silicon

A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

An electro-optic device includes a substrate and a waveguide on the substrate. The waveguide includes a layer stack including a plurality of electro-optic material layers interleaved with a plurality of interlayers, a waveguide core adjacent to the layer stack, a waveguide cladding layer, and a pair of electrodes in electrical contact with the plurality of electro-optic material layers. The plurality of interlayers maintains a first lattice structure at room temperature and a cryogenic temperature. The plurality of electro-optic material layers maintains a second lattice structure and crystallographic phase at the room temperature and the cryogenic temperature.

Method and system for formation of stabilized tetragonal barium titanate

Embodiments of the present invention are directed to reducing the effective capacitance between active devices at the contact level. In a non-limiting embodiment of the invention, an interlayer dielectric is replaced with a low-k material without damaging a self-aligned contact (SAC) cap. A gate can be formed over a channel region of a fin. The gate can include a gate spacer and a SAC cap. Source and drain regions can be formed adjacent to the channel region. A contact is formed on the SAC cap and on surfaces of the source and drain regions. A first dielectric layer can be recessed to expose a sidewall of the contact and a sidewall of the gate spacer. A second dielectric layer can be formed on the recessed surface of the first dielectric layer. The second dielectric layer can include a dielectric material having a dielectric constant less than the first dielectric layer.

Contact interlayer dielectric replacement with improved SAC cap retention

A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.

Methods of forming air gaps between source/drain contacts and the resulting devices

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Fremont, CA, United States of America

Vimal Kumar Kamineni