Intel Corporation

Vimal K Natarajan

David Zimmerman

Darshan Kobla

John C Johnson

A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.

Built-in self-test for stacked memory architecture

A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.

Generic address scrambler for memory circuit test engine

A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.

Generic data scrambler for memory circuit test engine

An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or more layers of dynamic random-access memory (DRAM) and a system element coupled with the memory stack, the system element including a memory controller for control of the memory stack, and repair logic that is coupled with the memory controller. The repair logic is to hold repair addresses that are identified as failing addresses for defective areas of the memory stack, with the repair logic to receive a memory operation request and implement redundancy repair for an operation address for the request using a repair logic memory to store the repair addresses and data for the repair addresses.

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Portland, OR, United States of America

Vimal K Natarajan