Advanced Micro Devices Corporation

Vilas K Sridharan

Sudhanva Gurumurthi

James Michael O'Connor

Gabriel H Loh

Yasuko Eckert

James Raymond Magro

Kedarnath Balakrishnan

Michael Ignatowski

Dean A Liberty

David Andrew Roberts

John Kalamatianos

Sergey Blagodurov

Manish Satyapal Gupta

Nuwan S Jayasena

Kevin Michael Lepak

Mark Donald Hill

Shaizeen Dilawarhusen Aga

Srilatha Manne

Amitabh Mehra

Alexander Lyashevsky

Ross Voigt La Fetra

Francisco Leonel Duran

Shrikanth Ganapathy

Magiting M Talisayon

Hanbing Liu

Lena E Olson

Sankaranarayanan Gurumurthy

Srikanth Masanam

Divya Madapusi Srinivas Prasad

Jeffrey Richard Rearick

Vikram Ramachandra

Shidhartha Das

Alex W Schaefer

Vydhyanathan Kalyanasundharam

David S Christie

Michael T Clark

Amit P Apte

Steven E Raasch

Mitesh Ramesh Meswani

Robert Gelinas

Jaewoong Sim

Daniel I Lowell

Jelena Ilic

Majed Valad Beigi

Cristian Constantinescu

Johnsy Kanjirapallil John

Phillip E Nevius

James R Williamson

Taniya Siddiqua

Balatripura S Chavali

Carlos Vallin

Mark E Wilkening

An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for detecting and mitigating silent data corruptions via adaptive voltage-frequency scaling

An exemplary computing device comprises an in-band processor and an out-of-band controller. The exemplary computing device also comprises a machine check architecture that includes a pipeline and a plurality of error detectors. The error detectors are configured to detect errors that occur in a plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for out-of-band logging and delivery of error reports

Devices, systems, and methods for out-of-band delivery of error reports

A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

Page retirement techniques for multi-page DRAM faults

A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.

Method and apparatus for fault prediction and management

An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.

Devices, systems, and methods for injecting fabricated errors into machine check architectures

An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.

Remote scalable machine check architecture

An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). When a host processor in the first partition detects an error that requires information from processor cores of the second partition, the host processor generates an access request with a target address pointing to a storage location in a memory of the second partition, not the first partition. When the host processor receives the requested error log information from the second partition, the host processor completes processing of the error. To support the host processor in generating the target address for the access request, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor.

Scalable machine check architecture

A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

Host-level error detection and fault correction

Selecting an error correction code type for a memory device includes: selecting, by the memory device in dependence upon predefined selection criteria, one of a plurality of error correction code types and carrying out memory access requests utilizing the selected error correction code type.

Selecting an error correction code type for a memory device

A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term 'ECC implementation' refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.

Error detection and correction in memory modules using programmable ECC engines

Error handling for resilient software includes: receiving data indicating a region of resilient memory; detecting an error associated with a region of memory; and preventing raising an exception for the error in response to the region of memory falling within the region of resilient memory by preventing the region of memory as being identified as including the error.

Error handling for resilient software

A memory controller includes a memory channel controller adapted to receive memory access requests and dispatch associated commands addressable in a system memory address space to a non-volatile storage class memory (SCM) module. The non-volatile error reporting circuit identifies error conditions associated with the non-volatile SCM module and maps the error conditions from a first number of possible error conditions associated with the non-volatile SCM module to a second, smaller number of virtual error types for reporting to an error monitoring module of a host operating system, the mapping based at least on a classification that the error condition will or will not have a deleterious effect on an executable process running on the host operating system.

Error reporting for non-volatile memory modules

A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

Method for a reliability, availability, and serviceability-conscious huge page support

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Boxborough, MA, United States of America

Vilas K Sridharan