Emc IP Holding Company LLC

Juniper Networks, Inc.

Oracle International Corporation

Vikram Venkataraghavan

Bruce Alexander Wilford

Mark Himelstein

Vishwas Durai

Rick Carlson

Richard Van Gaasbeck

Todd Wilde

Blair Barnett

Kevin J Rowett

Jaspal Kohli

James Yarbrough

Junxiao He

Prabakar Sundarrajan

Mohammed Zubair Visharam

David R Emberson

Michael Nishimoto

Kumar Narayanan

Ming Fung Wong

Grace Ho

Bill Katz

Shreyas Shah

Ariel Cohen

Gerald Cheung

Jonathan Davar

Daniel Arai

Ganesh Sundaresan

Cheng Tang

Greg Lockwood

Dan Arai

Naveed Cochinwala

Pierre Aulagnier

Mike Dvorkin

Junxiao (Max) He

Rich Van Gaasbeck

Abhinav Anand

Susheel Tadikonda

Vipul Jain

A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Multiprocessor system with independent direct access to bulk solid state memory resources

According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Exabyte-scale data processing system

Data processing system with a scalable architecture over ethernet

According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Non-uniform memory access (NUMA) mechanism for accessing memory with cache coherence

According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Flash memory complex with a replication interface to replicate data to another flash memory complex of a data processing system

A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Software-implemented flash translation layer policies in a data processing system

Methods and apparatus are provided for transferring data between servers and a remote entity having multiple peripherals. Multiple servers are connected to a remote entity over an Remote Direct Memory Access capable network. The remote entity includes peripherals such as network interface cards (NICs) and host bus adapters (HBAs). Server descriptor rings and descriptors are provided to allow efficient and effective communication between the servers and the remote entity.

Efficient data transfer between servers and remote peripherals

A method and apparatus stores media content in a variety of storage devices, with at least a portion of the storage devices having different performance characteristics. The system can deliver media to a large number of clients while maintaining a high level of viewing experience for each client by automatically adapting the bit rate of a media being delivered to a client using the client's last mile bit rate variation. The system provides clients with smooth viewing of video without buffering stops. The client does not need a custom video content player to communicate with the system.

Adaptive network content delivery system

Methods and apparatus are provided for virtualizing port adapter resources such as network interface cards (NICs) used to connect servers to packet based networks. Resources are offloaded from individual servers onto a resource virtualization switch. Servers connected to the resource virtualization switch using an I/O bus connection share access to NICs. Redundancy can be provided using multipathing mechanisms implemented at individual servers or high availability mechanisms implemented at the resource virtualization switch. Switchover can occur between ports on the same port adapter, between ports on separate adapters, or between ports on separate resource virtualization switches.

High availability and I/O aggregation for server environments

A device receives, from a client device, a request for a resource that is available from an origin device, and determines whether the resource is cached in a cache server or not cached in the cache server. The device forwards the request to the cache server regardless of whether or not the resource is cached in the cache server, and receives, when the resource is not cached in the cache server, a redirect command from the cache server based on the request. The device forwards the received redirect command to the client device, where the redirect command instructs the client device to obtain the resource from the origin device. The device receives, from the cache server and based on the request, the resource when the resource is cached in the cache server, and forwards the received resource to the client device.

Modular transparent proxy cache

Growing community of inventors

Saratoga, CA, United States of America

Vikram Venkataraghavan