Texas Instruments Corporation

Vikram N Doshi

Richard L Guldi

Takayuki Niuya

Shawn T Walsh

Ming Yang

Dong Joo Bae

James M Drumm

Hiro Tomomatsu

Hiroshi Ono

Hayato Deguchi

Roy D Clark

Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer.

Method of reducing channeling of ion implants using a sacrificial scattering layer

A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (,) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (,) are disposed. A silicon nitride layer (,) is in place below the BPSG layer (,), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (,) during high temperature processes such as reflow and densification of the BPSG layer (,) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (,) and the silicon nitride layer (,) using a two-step etch process. The first etch selectively etches silicon dioxide relative to silicon nitride, and thus stops on silicon nitride layer (,); besides serving as an etch stop, silicon nitride layer (,) protects underlying active regions (,) from damage that may be caused by ionized oxygen released during oxide etch. A brief nitride etch is then used to clear silicon nitride layer (,), without damaging comer locations (NC) of the sidewall structures (,).

Silicon nitride dopant diffusion barrier in integrated circuits

A method of filtering a bath (,) having a liquid containing particles of varying sizes therein and the recirculation and filtering system. The method and system require providing a recirculation route from the bath outflow and returning to the bath inflow. The route includes a first path communicating with the bath outflow and having serially a first controllable valve (,) and a filter having a relatively large pore size. The route also includes a second path communicating with the bath outflow and having serially a second controllable valve (,) and a filter having a relatively small pore size. There is a return path from each filter to the bath inflow. The return path from each filter can be a separate path or the paths can be connected at the output end before returning to the bath. The particle count in the recirculation route can be monitored either between the bath outflow and the first and second valves (,), between the bath inflow and each of the filters having large and small pore size (,), or both for controlling operation of the first and second valves. The controllable valves can also be controlled by a time program, bath operation program or the like.

Method for efficient filtration of chemical baths

Hydrofluoric acid (HF) mixed with water and often buffered with ammonium fluoride is a standard silicon dioxide wet etchant which is followed by a rinse. An improved silicon dioxide etch is vapor HF which may be followed by a water vapor rinse. The invention discloses a further improved silicon dioxide etch. Following an initial exposure to vapor HF for oxide removal, a first insitu water rinse occurs. A second exposure to vapor HF then occurs and is followed by a second insitu water rinse. Water, rather than water vapor, aids in freeing particles from the wafer surface. During both the water rinses, the wafer may be rotated at increasing speeds to aid in sweeping particles from wafer surface. The process may be practiced in a commercially available reactor and is suitable for ULSI devices having complex topographies, such as, for example, 64 megabit DRAMs employing crown type memory cells.

Two step oxide removal for memory cells

A technique for reducing active area encroachment (birdsbeak) by using a polysilicon hard mask combined with both wet and dry etch for the isolation nitride. This process forms a thinner layer of nitride adjacent the openings for oxide growth, which reduces stress at the silicon/nitride interface. The advantages include control over birdsbeak, reliable gate oxide quality, low junction leakage current, an improved active area, improved isolation, low peripheral junction leakage, and higher field transistor threshold voltage.

Growing community of inventors

Plano, TX, United States of America

Vikram N Doshi