Broadcom Corporation

Other

Intel Corporation

Vikram Gupta

Ed Lambert

Dan Wheeler Patterson

Peter J DesRosier

An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing.

Apparatus and method for preventing configurable system-on-a-chip integrated circuits from beginning I/O limited

Apparatus and method for preventing configurable system-on-a-chip integrated circuits from becoming I/O limited

A request from a first processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the first processor at a first clock frequency. A request from a second processor for access to a shared resource in a computing system is received, and access is provided to the shared resource by the second processor at a second clock frequency that is lower than the first clock frequency.

Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application

Various embodiments are disclosed relating to power-efficient techniques for invoking a co-processor. In an example embodiment, a computer system may include a first processor (e.g., a host processor) and a second processor (e.g., a co-processor). The first processor may instruct the second processor to perform an operation repeatedly on a data stream. The first processor may be placed in a low power state. The second processor may perform the operation repeatedly on the data stream while the first processor remains in the low-power state.

Power-efficient technique for invoking a co-processor

A method for designing an integrated circuit having analog and digital circuit portions is disclosed. The method involves providing an emulation circuit, which preferably comprises a number of gates equivalent to a number of gates in the digital circuit portion, affixing the emulation circuit on a test substrate together with a version of the analog circuit portion having at least some of the defined functions of the analog circuit portion, and then testing the analog circuit version.

Apparatus for designing mixed signal integrated circuits and configurable synchronous digital noise emulator circuit

Method for designing mixed signal integrated circuits and configurable synchronous digital noise emulator circuit

An electronic component for failure detection and analysis of bus activity comprises configuration circuitry, a buffer, and read circuitry. The configuration circuitry, the buffer, the read circuitry and the bus being tracked are on the same die. The configuration circuitry identifies one or more modes, one or more triggers, and one or more responses associated with the triggers. The buffer stores transactions on a bus according to the configuration circuitry. The read circuitry reads data from the buffer. A method of tracking bus activity comprises configuring a bus activity tracking component; monitoring an interface for a trigger event; and performing associated responses upon the occurrence of the trigger event.

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Fremont, CA, United States of America

Vikram Gupta