Intel Corporation

Advanced Micro Devices Corporation

University of Massachusetts

Vikram B Suresh

Sanu K Mathew

Sudhir K Satpathy

Raghavan Kumar

Rafael Misoczki

Manoj R Sastry

Santosh Ghosh

Vinodh Gopal

Andrew H Reinders

James D Guilford

Manoj Sachdev

Vivek K De

Ram K Krishnamurthy

Mark A Anders

Russell J Schreiber

Himanshu Kaul

Harish Krishnamurthy

Zeshan A Chishti

Patrick Koeberl

Rosario Cammarota

Neeraj S Upasani

Xiaosen Liu

David Wheeler

Avinash Laxmisha Varna

Wayne Burleson

Shashank Shekhar

Arvind Singh

Tao Zhou

Amitkumar Patel

Methods and apparatus relating to techniques utilizing fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management are described. In an embodiment, a configurable compute tile comprising a plurality of cryptocurrency mining engines. Logic circuitry causes deactivation of one or more cryptocurrency mining engines from the plurality of cryptocurrency mining engines based at least in part on a request for deactivation of the one or more cryptocurrency mining engines. The logic circuitry adjusts a nonce search resolution for one or more active cryptocurrency mining engines of the plurality of cryptocurrency mining engines in response to the request for deactivation. Other embodiments are also disclosed and claimed.

Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management

Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

Technologies for memory and I/O efficient operations on homomorphically encrypted data

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

Low latency post-quantum signature verification for fast secure-boot

Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

Combined SHA2 and SHA3 based XMSS hardware accelerator

In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

Accelerators for post-quantum cryptography secure hash-based signing and verification

In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

Odd index precomputation for authentication path computation

A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

Secure PUF-based device authentication using adversarial challenge selection

In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.

Technology for generating a keystream while combatting side-channel attacks

In one example an apparatus comprises accelerator logic to pre-compute at least a portion of a message representative, hash logic to generate the message representative based on an input message, and signature logic to generate a signature to be transmitted in association with the message representative, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and determine whether the message representative satisfies a target threshold allocation of computational costs between a cost to generate the signature and a cost to verify the signature. Other examples may be described.

Fast XMSS signature verification and nonce sampling process without signature expansion

Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (V) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.

Method and apparatus to provide memory based physically unclonable functions

A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

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Hillsboro, OR, United States of America

Vikram B Suresh