Real Intent, Inc.

Vikas Sachdeva

Pranav N Ashar

Prakash Narain

Vishnu Vimjam

Fabrice Baray

Hari Mony

Paul Vyedin

Nikhil Rahagude

Methods and systems are described to identify potential failures caused by metastability arising from signal propagation between asynchronous clock domains in integrated circuits with multiple operating modes, each mode allowing selected clocks to propagate. Typical integrated circuits have numerous operating modes, and hence numerous possible clock combinations, each combination causing different asynchronous clock-domain crossings, and hence different potential failures. Since verification for even one clock combination is time-consuming, explicitly enumerating and verifying all possible clock combinations is unviable. In practice very few clock combinations are verified, possibly missing failures. The present invention achieves superior performance, scalability, comprehensiveness and precision in verification despite numerous operating modes, due the following insights: (a) The number of possible clock combinations for a transmit-receive signal pair is small relative to the total number of operating modes, and (b) Cause of failure for a transmit-receive pair remain identical across many clock combinations associated with it.

Methods for identifying integrated circuit failures caused by asynchronous clock-domain crossings in the presence of multiple modes

Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed 'glitch') before settling to a final value consistent with the input values being applied to said logic circuit. An IC is likely to function erroneously, referred to as having a 'glitch failure', when a glitch value is observed at an output or captured by a storage element. Glitch failures are difficult and expensive to diagnose in a manufactured IC. To raise the productivity of IC development, it is imperative that any potential glitch failure in an IC be detected prior to manufacture. Said detection is hard because a typical IC has a very large number of logic circuits to analyze for glitch failure. To be practical, said analysis must have high performance and high accuracy. Said high performance requiring that said analysis should complete in acceptable run time even for the largest ICs. Said high accuracy requires that said analysis should identify all potential for glitch failure (100% recall), and minimize the number of logic circuits erroneously reported as having glitch failure potential (high precision). Whereas the glitch phenomenon, the potential for glitch failure and methods for detecting glitch failures in pre-manufacture IC models are well known, achievement of high performance with high accuracy has not yet been addressed in prior art. Whereas conventional methods for glitch checking are inefficient and insufficiently accurate, the methods and systems described in the present invention achieve new levels of performance, scalability and accuracy in said detection of glitch failures in an IC. Said methods and systems are based on a novel dissection of glitch-checking requirements into a multiplicity of individual steps, which said steps executed in a systematic sequence deliver high performance and accuracy.

Methods and systems for efficient identification of glitch failures in integrated circuits

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Bengaluru, India

Vikas Sachdeva