Freescale Semiconductor,inc.

Vikas R Sheth

Mehul D Shroff

Mark Douglas Hall

Brian J Fisher

Kurt H Junker

Jonathan L Cobb

James Edward Vasek

Jinmiao James Shen

Jin Miao Shen

William D Darlington

A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.

Treatment for reduction of line edge roughness

A method for forming a semiconductor device () includes forming an organic anti-reflective coating (OARC) layer () over the semiconductor device (). A tetra-ethyl-ortho-silicate (TEOS) layer () is formed over the OARC layer (). The TEOS layer () is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer () is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer () is formed over the TEOS layer () and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer () before applying photoresist, pattern defects are reduced.

Plasma treatment for surface of semiconductor device

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Austin, TX, United States of America

Vikas R Sheth