Qualcomm Incorporated

Vikas Mahendiyan

Yong Xu

Boris Andreev

Farrukh Aquil

Ravindra Arvind Khedkar

Jeffrey Mark Hinrichs

Patrick Isakanian

Satish Krishnamoorthy

Anand Meruva

Yuxin Li

A memory interface circuit includes a first receiver coupled to a differential data strobe signal and a second receiver that has a first input coupled to a reference voltage source and a second input coupled to one of the pair of complementary signals. A qualification circuit is configured to detect a preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state, detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state, and assert a preamble detection signal when the preamble transmission is detected. A gating circuit is configured to provide a receive clock signal when the preamble detection signal is asserted.

Read data capture for a high-speed double data rate interface

A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

Clock qualifier enhancement for external double data rate memory interfaces

A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

DDR phy parallel clock paths architecture

Growing community of inventors

San Diego, CA, United States of America

Vikas Mahendiyan