Qualcomm Incorporated

Vikas Kumar Sinha

Vedaraman Geetha

Amit Kumar

Ramkumar Srinivasan

Adrian Montero

Paul Kitchin

Sunil Oak

Antonio Priore

Nir Maor

Henry Stracovsky

Roshan Sreekumar Nair

Certain aspects of the present disclosure provide techniques and apparatus for translation lookaside buffer (TLB) compression. Embodiments include determining that a plurality of physical memory addresses, associated with a plurality of virtual memory addresses, are contiguous with one another and share one or more common address bits or one or more common attribute bits, wherein each respective physical memory address of the plurality of physical memory addresses corresponds to a separate respective physical memory page. Embodiments include generating a tag for an entry in a TLB, the tag representing the plurality of virtual memory addresses. Embodiments include associating, in the entry in the TLB, the tag with data comprising: a single instance of the one or more common address bits or the one or more common attribute bits of the plurality of physical memory addresses; and other bits of the plurality of physical memory addresses.

Compressing data portions in a translation lookaside buffer

A method of explicit lockstep for functional safety includes spawning, by a main thread, a first safe thread core and a second safe thread core. The method also includes initializing and mapping a first data register associated with the first safe thread core to each safe variable of a set of predetermined safe variables. The method further includes initializing and mapping a second data register associated with the second safe thread core to each safe variable of the set of predetermined safe variables. The method also includes comparing, by a hardware comparator, a first safe variable value in the first data register to a second safe variable value in the second register. The method further includes issuing an error completion to the first safe thread core and the second safe thread core when the hardware comparator detects a mismatch between the first data register and the second data register.

Explicit lockstep for functional safety

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Methods and systems for memory bandwidth control

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality of memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

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Austin, TX, United States of America

Vikas Kumar Sinha