Texas Instruments Corporation

Vikas Kumar Sinha

Sandeep Kesrimal Oswal

Nitin Kumar Agarwal

Jayawardan Janardhanan

Anand Hariraj Udupa

Sujoy Chakravarty

Visvesvaraya Appala Pentakota

Karthik Subburaj

Krishnaswamy Nagaraj

Anant Shankar Kamath

Sudheer Kumar Vemulapalli

Somasunder Kattepura Sreenath

Gopalkrishna Nayak

Shivaprakash Halagur

Visvesvararaya A Pentakota

Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs.

Phase interpolator and a delay circuit for the phase interpolator

A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

Synchronous clock multiplexing and output-enable

A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.

Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)

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Karnataka, India

Vikas Kumar Sinha