Toshiba Memory Corporation

Integrated Device Technology, Inc.

Nvidia Corporation

Renesas Electronics America Inc.

Vikas Kumar Agrawal

Feng Qiu

Nidish Ramachandra Kamath

Sridhar Krishnamurthy

Jay Chieh Chen

John C Hsu

Binh Pham

Chi Keung Lee

Cheng Wen Hsiao

Umang Shah

David Stanley Maxey

David Stanely Maxey

Shrivathsa Bhargavravichandran

Yimu Guo

Apparatuses, systems, and methods for implementing a multi-driver architecture are described. The multi-driver architecture may include a first driver and a second driver configured to receive an input voltage. A predriver logic circuit may select one of the first driver and the second driver to convert the input voltage into an output voltage. A controller may be connected to the first driver and the second driver, and a switch may be connected between an output terminal of the first driver and the controller. The controller may be configured to control an internal resistance of the switch. In response to the first driver being selected by the predriver logic circuit, the first driver may output the output voltage at a constant impedance level.

Apparatus for multi-driver architecture with high voltage protection and impedance control

A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.

DDR storage adapter

An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit and a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches. The logic control circuit is configured to activate either the LVDS output circuit or the HCSL output circuit.

Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use

An integrated circuit comprising, a voltage regulator circuit and a programmable low power high-speed current steering logic (LPHCSL) driver circuit coupled to a common supply voltage. The voltage regulator circuit includes a native source follower transistor having a negative threshold voltage to provide more headroom for the voltage regulator to operate. The LPHCSL driver circuit includes a plurality of selectable output driver legs and a plurality of programmable resistors. The ability to use a common supply voltage and the ability to select multiple output impedance drivers reduces the die area without increasing the complexity of the integrated circuit.

Programmable low power high-speed current steering logic (LPHCSL) driver and method of use

A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.

Hierarchical pushdown of cells and nets to any logical depth

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San Jose, CA, United States of America

Vikas Kumar Agrawal