Astera Labs, Inc.

Asiera Labs, Inc.

Vikas Khandelwal

Pulkit Khandelwal

Casey Morrison

Ken (Keqin) Han

Charan Enugala

Enrique Musoll

Jitendra Mohan

Subbarao Arumilli

Vivek Trivedi

Chi Feng

An integrated-circuit retimer selectively logs information corresponding to mission-mode data, received and transmitted via counterpart high-bandwidth data interfaces, in real-time and accordance with contents of a logging control storage written by an external component during retimer run time.

Retimer with host-interactive data logging engine

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Low-latency retimer with seamless clock switchover

A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Low-latency signaling-link retimer

Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Configurable-aggregation retimer with media-dedicated controllers

Growing community of inventors

San Jose, CA, United States of America

Vikas Khandelwal