Texas Instruments Corporation

Vikas K Agrawal

Bryan David Sheffield

Stephen Wayne Spriggs

George B Jamison

Eric L Badi

David J Toops

Tam Minh Tran

M Dwayne Ward

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Self-clocking memory device

Method of operating a memory at high speed using a cycle ready status output signal

Cycle ready circuit for self-clocking memory device

According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.

Method and system for power conservation in memory devices

A memory timing architecture which very accurately tracks the read and write timing of a memory over a wide range of array sizes, with separate read and write timing circuits. The read reset circuitry uses a plurality of dummy cells to gauge the time necessary to complete the read operation, while the write reset uses a single dummy cell to gauge the time necessary to complete the write operation. These circuits provide for a more accurately-timed feedback signal, which allows for increased speed while at the same time reducing power consumption and heat buildup.

Self-timed memory reset circuitry

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Dallas, TX, United States of America

Vikas K Agrawal