Imec Vzw

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Vikas Dubey

Eric Beyne

Ingrid De Wolf

Francky Catthoor

Jef Poortmans

Jaber Derakhshandeh

Giovanni Capuz

Hans Goverde

Christiaan Baert

A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

Method for bonding semiconductor chips to a landing wafer

A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.

Simulation of photovoltaic modules

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

Method for self-aligned solder reflow bonding and devices obtained thereof

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

Method for aligning micro-electronic components

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Leuven, Belgium

Vikas Dubey