Stmicroelectronics International N.v.

Vikas Chelani

Ankur Bal

An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.

Clock delay circuit for chip reset architecture

A debounce circuit and a method for masking or filtering a glitch from an input signal are provided. The debounce circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives the input signal, detects a glitch in the input signal and outputs one or more reset synchronizer output signals having a first reset synchronizer state indicating detection of the glitch. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating detection of the glitch and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, keeps an output signal of the debounce circuit in a present state of the output signal of the debounce circuit.

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Noida, India

Vikas Chelani