Arm Limited

International Business Machines Corporation

Meta Platforms, Inc.

Meta Platforms Technologies, LLC

Facebook Technologies, LLC

Vikas Chandra

Robert Campbell Aitken

Mudit Bhargava

Brian Tracy Cline

Sarika Sinha

Liangzhen Lai

Lucian Shifren

Shidhartha Das

Bal S Sandhu

Sachin Satish Idgunji

Azeez Jennudin Bhavnagarwala

Saurabh Pijuskumar Sinha

Ganesh Venkatesh

Cezary Pietrzyk

Gary Dale Carpenter

George McNeil Lattimore

James Edward Myers

Ingrid Anda Cotoros

Parameshwarappa Anand Kumar Savanth

John Philip Biggs

Pierce I-Jen Chuang

Greg Yeric

Andy Wangkun Chen

Paul Gilbert Meyer

Srinivasan S Muthuswamy

Harshit Khaitan

Gregory Munson Yeric

Joel Thornton Irby

Meng Li

Yu Hsin Chen

Rakesh Ranjan

Naveen Suda

Daeyeon Kim

Satyanand Vijay Nalam

Gabriel Molina

Yuchen Fan

Xiaoyu Xiang

Lele Wang

Chakravarty Reddy Alla Chaitanya

Peter Beshay

Mihir Rajanikant Choudhury

One embodiment of the present invention sets forth a technique for combining a color image and a monochrome image. The technique includes inputting a first set of pixel values from the color image and a second set of pixel values from the monochrome image into a neural network. The technique also includes applying, via a first set of neural network layers, one or more downsampling operations and one or more upsampling operations to feature maps associated with the inputted pixel values to generate a first output image that includes a first set of color values for a first set of pixel locations in the monochrome image. The technique further includes applying a second set of neural network layers to the first set of color values to generate a second output image that includes a second set of color values that is larger than the first set of color values.

Fusion and super-resolution of monochrome and color images using deep neural networks

In one embodiment, a method includes accessing a video captured by cameras which is associated with a first framerate lower than a threshold framerate, for any two adjacent frames of the accessed video: generating a warped frame from the two adjacent frames based on an optical flow associated with the two adjacent frames, determining alignments for the two adjacent frames, respectively, fusing the determined alignments for the two adjacent frames, and generating a reconstructed frame based on the fused alignment, and reconstructing the accessed video based on the any two adjacent frames and their respective reconstructed frames, wherein the reconstructed video is associated with a second framerate higher than the threshold framerate.

Video reconstruction from videos with ultra-low frame-per-second

In one embodiment, a method for machine learning acceleration includes receiving instructions to perform convolution on an input tensor using a filter tensor, determining that the size of a first dimension of the input tensor is less than a processing capacity of each of multiple subarrays of computation units in a tensor processor, selecting a second dimension of the input tensor along which to perform the convolution, selecting, based on the second dimension, one or more dimensions of the filter tensor, generating (1) first instructions for reading, using vector read operations, activation elements in the input tensor organized such that elements with different values in the second dimension are stored contiguously in memory, and (2) second instructions for reading weights of the filter tensor along the selected one or more dimensions, and using the first and second instructions to provide the activation elements and the weights to the subarrays.

Flexible compute array utilization in a tensor processor

In one embodiment, a method for machine learning acceleration includes receiving, by a shared controller of a tensor processor cluster that includes multiple tensor processors, a multi-cycle instruction, determining, based on the instruction, a sequence of vector operations to be executed by the tensor processors and address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation. The method also includes, for each vector operation in the sequence, generating, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition on which the tensor processor is to operate, multicasting the common address offset to the tensor processors, and controlling the tensor processors to execute the vector operation in parallel and in lock step.

Spatial tiling of compute arrays with shared control

Disclosed herein is a method for using a neural network across multiple devices. The method can include receiving, by a first device configured with a first one or more layers of a neural network, input data for processing via the neural network implemented across the first device and a second device. The method can include outputting, by the first one or more layers of the neural network implemented on the first device, a data set that is reduced in size relative to the input data while identifying one or more features of the input data for processing by a second one or more layers of the neural network. The method can include communicating, by the first device, the data set to the second device for processing via the second one or more layers of the neural network implemented on the second device.

Systems and methods for distributing a neural network across multiple computing devices

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

CES-based latching circuits

An approach is provided for predicting an exception during a debugging of software code before the debugging encounters the exception. During a debugging of a line number L of the code and based on an exception being predicted to be encountered at a line number M, a warning is displayed that the exception is to be encountered at the line number M, which is within a range of line numbers L+1 through L+X, where L&#x3e;0 and X&#x3e;1. Using a fix written in response to the predicted exception, the software code is modified. During a debugging of the line number M of the code, the modified software code is executed to avoid the predicted exception.

Exception prediction before an actual exception during debugging

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

System and method for supporting alternate number format for efficient multiplication

Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.

Spiking neural network

A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

Method and apparatus for memory wear leveling

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.

Logic encryption using on-chip memory cells

A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

Circuit and method for configurable impedance array

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Correlated electron switch programmable fabric

Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to compensating for integrated circuit manufacturing process variation with correlated electron switch devices.

Process variation compensation with correlated electron switch devices

Disclosed are a circuit and method for implementing a switching function. In an embodiment, the circuit includes a first logic circuit, a second logic circuit, and a Correlated electron switch (CES) element. The CES element is configurable to have a non-volatile state to enable or disable an electrical connection between the first logic circuit and the second logic circuit.

Correlated electron switch device

Growing community of inventors

Fremont, CA, United States of America

Vikas Chandra