Freescale Semiconductor,inc.

Vikas Ahuja

Sourav Roy

Anupam Singal

Mathur Ashish

Batmanabhan Purushothaman

Shourjo Banerjee

Meenakshi Vasisht

A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.

Data cache prefetch controller

A method of transitioning between an active mode and a power-down mode in a processor-based system includes saving a state of the active mode, detecting the occurrence of one or more interrupt events during a transition between the active mode and the power-down mode, and responding to the detected interrupt events.

Method of transitioning between active mode and power-down mode in processor based system

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Delhi, India

Vikas Ahuja