Micron Technology Incorporated

Micron Semiconductor, Inc.

Viju K Mathews

Pierre C Fazan

Nanseng Jeng

Gurtej S Sandhu

Trung Tri Doan

Charles H Dennison

Mark E Tuttle

Werner Juengling

Guy T Blalock

Randhir P Thakur

Thomas Arthur Figura

Ardavan Niroomand

Hiang C Chan

Chang Jun Yu

Charles L Turner

Akram Ditali

Mohammed Anjum

Roy L Maddox, Iii

Roy Maddox

An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the electrode in a lower region of a substrate opening. The method may further include forming a second portion of the electrode in the opening and overlying the first portion, the insulative layer encompassing a sidewall of the second portion. The method may further include forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein the first portion and the second portion are different materials. In an embodiment, the second portion is a diffusion barrier layer and the third portion is an oxidation resistant layer. In an embodiment, the method includes encompassing a lower sidewall of the third portion with the insulative layer.

Storage cell capacitor compatible with high dielectric constant materials

A field isolation process performed on a silicon wafer is carried out by high pressure oxidation. Using oxygen rather than water vapor as the oxidant substantially eliminates nitride inclusions via the Kooi effect. Preferred high pressure field oxidation processes simplify all CMOS flows by eliminating the need for sacrificial oxide growth and removal steps.

Streamlined field isolation process

A method of forming isolation structures in semiconductor substrates comprising exposing a region of the semiconductor simultaneously to a transforming agent and to a viscosity reducing agent so that the transforming agent transforms a portion of the substrate into an isolation structure and the viscosity reducing agent reduces the viscosity of the isolation structure during formation. In one embodiment, a silicon substrate is exposed to oxygen in the presence of fluorine so that a silicon oxide isolation region is formed. The fluorine reduces the viscosity of the silicon oxide isolation region during formation which results in less lateral, bird's beak encroachment under adjacent masking stacks and also results in lower internal stress in the isolation region during formation. The lower internal stress and the lessened lateral encroachment result in thicker and improved isolation regions.

Semiconductor wafer isolation structure formed by field oxidation

Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises, polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material. During the filling of the undercut region, at least some of the mass or spacer is oxidized to form a bump over the bird's beak region. Oxide material is then removed from over the active area with such removal reducing the size of the bump. A gate dielectric layer can then be provided over the active area.

Methods of forming field oxide and active area regions on a semiconductor substrate

Formation of a structure of a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed oh the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.

Interconnect structure having improved resist adhesion

Process to improve the flow of oxide during field oxidation by fluorine doping

Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material. During the filling of the undercut region, at least some of the mass or spacer is oxidized to form a bump over the bird's beak region. Oxide material is then removed from over the active area with such removal reducing the size of the bump. A gate dielectric layer can then be provided over the active area.

Methods of forming field oxide and active area regions on a semiconductive substrate

A semiconductor processing method of forming an electrically conductive contact plug relative to a wafer includes, a) providing a substrate to which electrical connection is to be made; b) depositing a layer of first material atop the substrate to a selected thickness; c) pattern masking the first material layer for formation of a desired contact opening therethrough; d) etching through the first material layer to form a contact opening therethrough for making electrical connection with the substrate, the contact opening having an outermost region; e) after etching to form the contact opening, removing the masking from the first material layer; f) after removing the masking from the first material layer, facet sputter etching into the first material layer relative to the contact opening to provide outwardly angled sidewalls which effectively widen the contact opening outermost region, the outwardly angled sidewalls having an inner base where they join with the original contact opening; g) depositing a layer of conductive material atop the wafer and to within the facet etched contact opening to fill the contact opening; and h) etching the conductive material and first material layer inwardly to at least the angled sidewalls' inner base to define an electrically conductive contact plug which electrically connects with the substrate.

Semiconductor processing method of forming an electrically conductive contact plug

A method for use in patterning a conductive layer of an integrated circuit includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide region is formed on the titanium nitride layer. A photoresist layer is formed on the oxide region for use in patterning the conductive layer. The oxide region may be formed by oxidation of the titanium nitride layer or by depositing an oxide layer on the titanium nitride layer.

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Boise, ID, United States of America

Viju K Mathews