Lsi Logic Corporation

Lsi Corporation

Tritech Microelectronics, Ltd

Vijendra Kuroodi

Geeta K Desai

Eric Hung

Mirko Dusan Vojnovic

Alexander Miretsky

Remi C Lenoir

An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer. Thus, an overall electronic system is formed having a board with no more than two conductive layers, an execution engine that receives a first clock signal, a memory controller which receives a second clock signal, and a memory device that sends data to and from the memory controller at twice the rate of the second clock signal. Using a throttled second clock signal allows for less expensive packaging and mounting of packaged integrated circuits on a less expensive PCB, while still maintaining use of a DDR DRAM transfer mechanism.

Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board

Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board

A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate. By selectively clocking the memory controller at different clocking rates, the memory controller need not be modified in hardware, yet can accommodate different memory devices by allowing a user to simply plug one type of memory into a receptacle rather than another depending on the cost constraints and user application. Therefore, the memory controller is adaptable during a power-on reset in which the computer system is initialized to automatically receive and control different types of memory selected by a user.

Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits

A semiconductor memory device is provided as well as a method for operating the semiconductor memory device. The memory device includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell of the NOR array involves a single transistor, similar to each cell of the NAND array. The memory device is, therefore, an integrated circuit that includes not only the NOR and NAND arrays, but also the row and column decoders corresponding to each array. Furthermore, the integrated circuit includes the interface circuitry needed to transfer information as pages into and from the NAND array. The corresponding interface or controller is implemented on the same monolithic substrate as both the NAND array and the NOR array. Addresses targeted for the NOR array are sent as fully memory-mapped data into the NOR array, whereas addresses targeted for the NAND array are sent through the controller integrated within the semiconductor memory device. The single transistor cell of both the NAND array and NOR array preferably involves a flash EEPROM-type transistor that implements a floating gate dielectrically spaced between a control gate and the semiconductor substrate.

Integrated NAND and nor-type flash memory device and method of using the same

This invention describes a method and apparatus for filtering noise from a measurement of the X and Y coordinates of a resistive digitizer. The method applies to both four and five wire resistive digitizers biased with a DC voltage. The same filtering and measurement apparatus can be used on both types of digitizers with inclusion of an extra signal pin to accommodate the sense lead of the five wire digitizer. This approach involves connecting the signal to be read to a filter, reading the filtered voltage, and disconnecting the signal from the filter before disconnecting bias voltage from the planes of the digitizer. A separate filter is used for the X and Y coordinate signals and each filter voltage can be read at any time before the next measurement. A reset voltage is available to an established reference on the filter capacitor when a &ldquo;pen up&rdquo; status is detected.

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Cupertino, CA, United States of America

Vijendra Kuroodi