Dell Products Inc.

Vijender Kumar

Bhyrav M Mutnury

Mallikarjun Vasa

Douglas E Wallace

Malikarjun Vasa

Sukumar Muthusamy

Sunil Pathania

Ashish Shrivastava

Seema P K

An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Integrated thermal-electrical co-simulation

A printed circuit board (PCB) includes first and second signal pads and a guard trace formed on a surface of the PCB. The first and second signal pads are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal pad and the second signal pad. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.

Guard trace ground via optimization for high-speed signaling

An information handling system includes a first component including a transmitter for a high-speed serial data interface, and a second component including a receiver for the high-speed serial data interface. The receiver includes an equalization stage and a decision feedback equalization (DFE) stage. The equalization stage has an input to configure the equalization stage in one of a first low equalization state and a first high equalization state. The DFE stage has a plurality of tap inputs. The first component provides a plurality of training runs on the high-speed serial data interface. The second component receives the training runs, provides for each training run a set of tap settings for each tap input, determines whether or not a variation in the tap settings for the training runs is greater than a predetermined variation value, and, when the variation is greater than the predetermined variation value, sets the first input to configure the first equalization stage from the first low equalization state to the first high equalization state.

Link training scheme for high-speed serializer/deserializer

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Bengaluru, India

Vijender Kumar