The Penn State Research Foundation

Other

Vijaykrishnan Narayanan

Suman Datta

Xueqing Li

Sumeet Kumar Gupta

Rajeev Sharma

Namsoon Jung

Hankyu Moon

John Sampson

Sumitha George

Kaisheng Ma

Huichu Liu

Ramesh Vaddi

Ahmedullah Aziz

Kevin Maurice Irick

Nikhil Shukla

Alexandre Schmid

Ramakrishnan Krishnan

Unsuk Heo

Vinay Saripalli

Dheeraj Mohata

Saurabh Mookherjea

Jawar Singh

Saurabh Mookerjea

Nelson Daniel Troncoso Aldas

Harland Patch

Codey Mathis

Chonghan Lee

Moon Seok Kim

Eric Homan

Mahsa Shoaran

Christina Grozinger

An intelligent insect trap and identification system is disclosed. The intelligent insect trap and identification system can include an insect imaging chamber and identification system. The chamber can include a first cell for accepting insects, a second cell, a first reflector in the second cell, and a first imaging device in the second cell for recording one or more first visual images of the one or more insects in the first cell. Based on the image, the insect imaging chamber can detect and identify the insects. Other aspects, embodiments, and features are also claimed and described.

Intelligent insect trap and monitoring system

A sense amplifier utilizes a phase transition material (PTM) in conjunction with CMOS circuits to provide a precise sensing threshold. The sense amplifier can be used in memory applications to sense states of stored bits with high accuracy and robustness. In one sense amplifier, a first diode-connected transistor has gate and drain nodes coupled to an input node of the sense amplifier, a second transistor has a gate node coupled to the gate node of the first diode-connected transistor, and the PTM is coupled to the source node of the second transistor. In another sense amplifier, a first transistor has a gate node coupled to an input node of the sense amplifier, a PTM is coupled to the source node of the first transistor, and an output stage including an inverter is coupled between a drain node of the first transistor and an output node of the sense amplifier.

Low power sense amplifier based on phase transition material

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I&#x2212;Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

Nonvolatile digital computing with ferroelectric FET

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I-Vhysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two Istates at V=0.

Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.

Low power nanoelectronics

A power rectifier includes a stage having a first Tunneling Field-Effect Transistor ('TFET') having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed.

Power rectifier using tunneling field effect transistor

A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.

TFET based 4T memory devices

Memory devices and methods of operation are provided. A memory device includes first and second cross-coupled inverters and first and second access transistors coupled to an input node of the second inverter. The memory device also includes a control circuit for providing a first reference voltage at a first ground node of the first inverter and a second reference voltage at a second ground node of the second inverter. The first access transistor is configured to conduct current from a first bit line to the input node and to provide substantially no current conduction from the input node to the first bit line. The second access transistor is configured to conduct current from the input node to one of the first bit line and a second bit line and to provide substantially no current conduction from the input node to the one of first and second bit lines.

TFET based 6T SRAM cell

The present invention is an embedded audience measurement platform, which is called HAM. The HAM includes hardware, apparatus, and method for measuring audience data from image stream using dynamically-configurable hardware architecture. The HAM provides an end-to-end solution for audience measurement, wherein reconfigurable computational modules are used as engines per node to power the complete solution implemented in a flexible hardware architecture. The HAM is also a complete system for broad audience measurement, which has various components built into the system. Examples of the components comprise demographics classification, gaze estimation, emotion recognition, behavior analysis, and impression measurement.

Apparatus and method for measuring audience data from image stream using dynamically-configurable hardware architecture

The present invention is an apparatus and method for object recognition from at least an image stream from at least an image frame utilizing at least an artificial neural network. The present invention further comprises means for generating multiple components of an image pyramid simultaneously from a single image stream, means for providing the active pixel and interlayer neuron data to at least a subwindow processor, means for multiplying and accumulating the product of a pixel data or interlayer data and a synapse weight, and means for performing the activation of an accumulation. The present invention allows the artificial neural networks to be reconfigurable, thus embracing a broad range of object recognition applications in a flexible way. The subwindow processor in the present invention also further comprises means for performing neuron computations for at least a neuron. An exemplary embodiment of the present invention is used for object recognition, including face detection and gender recognition, in hardware. The apparatus comprises a digital circuitry system or IC that embodies the components of the present invention.

Apparatus and method for hardware implementation of object recognition from an image stream using artificial neural network

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State College, PA, United States of America

Vijaykrishnan Narayanan