Texas Instruments Corporation

Vijayalakshmi Devarajan

Richard Sterling Broughton

Richard Edwin Hubbard

Jingwei Xu

Gangqiang Zhang

Wesley Ray

Dushmantha Bandara Rajapaksha

Roland Sperlich

Anant Shankar Kamath

Gianpaolo Lisi

Ali Djabbari

Angelo William Pereira

Mark Edward Wentroble

Sri Navaneethakrishnan Easwaran

Kosha Mahmodieh

Vaibhav Garg

John H Carpenter, Jr

Shanmuganand Chellamuthu

Timothy Paul Duryea

Xiaochun Zhao

Benjamin Lee Amey

Lindsay Langford

Angelo W D Pereira

A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Data and power isolation barrier

A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

Lower-skew receiver circuit with RF immunity for controller area network (CAN)

A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Lead frame for multi-chip modules with integrated surge protection

A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals.

Bus transceiver with ring suppression

An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

Automatic input/output voltage control

An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Integrated circuit with combined interrupt and serial data output

An example apparatus includes a feedback loop to: change a direction value when a second current value is greater than a first current value, the second current value being obtained after the first current value; and maintain the direction value when the second current value is less than the first current value. When the direction value corresponds to a first direction value, a summer increases a reference signal by a step size. When the direction value corresponds to a second direction value different than the first direction value, the summer decrease the reference signal by the step size.

Methods and apparatus to increase efficiency for wireless power transfer

A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.

Current sink with negative voltage tolerance

A wireless resonant power transmitter includes a first half-bridge and a second half-bridge adapted to be class D driven that are coupled to drive a series resonant circuit including a primary inductor (L) having a high side terminal and a low side terminal, and primary capacitor (C). A peak voltage sensor that includes a summing block is coupled across the high side terminal and the low side terminal of the primary L, and a peak-to-peak voltage detector is coupled to an output of the summing block to generate a DC voltage signal that is proportional to a peak-to-peak voltage across the primary C.

Peak voltage detection in a differentially driven wireless resonant transmitter

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

VDS comparator rise P, fall P, on late, off late outputs for ZVC timing

Methods, apparatus, systems and articles of manufacture to efficiently transfer power wirelessly are disclosed. An example apparatus includes a feedback loop to when a second current value is greater than a first current value, change a direction value, the second current value being obtained after the first current value; when the second current value is less than the first current value, maintain the direction value; and a summer to when the direction value corresponds to a first direction value, increase a reference signal by a step size; and when the direction value corresponds to a second direction value different than the first direction value, decrease the reference signal by the step size.

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Plano, TX, United States of America

Vijayalakshmi Devarajan