Arm Limited

Vijaya Kumar Vinukonda

Ranabir Dey

Mikael Rien

Seshagiri Rao Bogi

Vinay Chenani

Fabrice Blanc

Mikael Yves Marie Rien

Abhinav Kumar

Kundan Srivastava

Kishan Chanumolu

Biswanath Nayak

Vikas Murli Kyatsandra

Various implementations described herein are related to a device having header circuitry with first transistors that are configured to receive a supply voltage and provide a dynamically biased voltage. The device may include reference generation circuitry having multiple amplifiers that are configured to receive the supply voltage and provide reference voltages based on the supply voltage. The device may include bias generation circuitry having second transistors configured to track changes in the dynamically biased voltage and adjust the dynamically biased voltage by generating bias voltages based on the reference voltages and by applying the bias voltages to the header circuitry so as to adjust the dynamically biased voltage.

Dynamic biasing techniques

Various implementations described herein are directed to a device having an output pad that provides an input-output (IO) voltage from an IO power supply. The device may include core ramp detection circuitry that detects a first ramp of a core voltage from a core power supply and provides a core ramp sensing signal. The device may include output logic circuitry that couples the output pad to ground after receiving the core ramp sensing signal so as to reduce leakage of the IO power supply.

Core ramp detection circuitry

An I/O ring formed by a single type of I/O cell. The I/O cell has a substantially square shape in which the height and width dimensions are substantially equal. Each I/O cell has an X-axis and a Y-axis, where the two or more I/O cells are mounted adjacent on an axis by flipping every alternate I/O cell about another axis to share a vertical bus between the two I/O cells. Each I/O cell has a power pin portion and a ground pin portion to be dimensioned to be approximately one-half a designated power pin region and ground pin portion, respectively.

System, method and apparatus for a single input/output cell layout

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Voltage level shifting circuitry

Briefly, embodiments of claimed subject matter relate to controlling a voltage across a circuit element utilized in a pre-driver for a bidirectional communications bus. In embodiments, a voltage control circuit may be utilized to reduce electrical stress across a capacitor coupled to the pre-driver to the communications bus. The voltage control circuit may operate to provide a voltage to a middle point between two capacitors, of a plurality of capacitors, which may operate to limit voltage across one or more capacitors to below a predetermined limit.

Circuit for controlling shape of a driver signal waveform

The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

Receiver circuitry and method for converting an input signal from a source voltage domain into an output signal for a destination voltage domain

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include signal generation circuitry that receives an input signal from a first voltage domain and generates multiple internal signals based on the input signal. The integrated circuit may include signal evaluation circuitry that receives the multiple internal signals from the signal generation circuitry and provides an intermediate signal based on the multiple internal signals. The integrated circuit may include signal conversion circuitry that receives the intermediate signal and provides an output signal for a second voltage domain based on the intermediate signal. The integrated circuit may include signal protection circuitry that receives the input signal from the first voltage domain, receives the intermediate signal from the signal evaluation circuitry, and allows the input signal until the intermediate signal transitions between a first state and a second state that is different than the first state.

Overdrive receiver circuitry

Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

Electrostatic discharge protection circuitry

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

General purpose receiver

Output signal generation circuitrymay be used for converting an input signalfrom a source voltage domain to an output signal for a destination voltage domain, the destination voltage domain operating from a supply voltage that exceeds a stressing threshold of components within the output signal generation circuitry. The output signal generation circuitry may comprise level shifting circuitryoperating from the supply voltage, which is configured to generate at an output nodethe output signal for the destination voltage domain in dependence on the input signal. The output signal generation circuitry may also comprise tracking circuitryA,B,C,D associated with at least one component of the level shifting circuitry to ensure that a voltage drop across the at least one component does not exceed the stressing threshold, wherein the tracking circuitry additionally introduces a delay in a change in the output signal in response to a change in the input signal. Timing compensation circuitryA,B may also be provided, to control the voltage on the output node in a manner to compensate for the delay introduced by the tracking circuitry.

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Bengaluru, India

Vijaya Kumar Vinukonda