Texas Instruments Corporation

Vijaya B P Sarathy

Robert John Cyran

Scott Paul Gary

Scott E Smith

Edward Alan Anderson

Thomas J Shepherd

Devendra Pradhan

Sukanya Venkatesan

Krishnan K Rama

An apparatus for sharing embedded analog-to-digital conversion resources across multiple hardware and software sample conversation queues includes an analog front end, a least one FIFO buffer, a plurality of configuration registers and a sequencer. The sequencer admits a higher priority hardware stepping sequence until the higher priority stepping sequence is completed. After completion, the apparatus reverts to completing pending conversions.

Sharing embedded ADC resources across hardware and software sample-conversion queues with improved availability of the resources

Systems and methods for improved power profiling of embedded applications are presented. These inventions provide the ability to measure the power consumption of an embedded application at the task level as the application is executing on the target hardware. Methods and apparatus are provided to permit such measurements in both real-time and non-real-time.

System and method for power profiling of tasks

Methods and systems are provided for developing a power management strategy for an application as the application is developed. These methods and systems broadly provide for building the application incorporating a power management module operable to provide several power management methods, capturing power consumption data of the application as it is executed on a target system, accepting modifications to the application to use one or more of the power management methods, and repeating these steps as needed. A power scaling library may also be incorporated in the application and the application may be modified to use the dynamic frequency and voltage scaling functionality provided by the power scaling library.

Methodology for coordinating and tuning application power

Methods and systems are provided for dynamically managing the power consumption of a digital system. These methods and systems broadly provide for varying the frequency and voltage of one or more clocks of a digital system upon request by an entity of the digital system. An entity may request that the frequency of a clock of the processor of the digital system be changed. After the frequency is changed, the voltage point of the voltage regulator of the digital system is automatically changed to the lowest voltage point required for the new frequency if there is a single clock on the processor. If the processor is comprised of multiple processing cores with associated clocks, the frequency is changed to the lowest voltage point required by all frequencies of all clocks.

Methods and systems for performing dynamic power management via frequency and voltage scaling

Methods and systems are provided for dynamically managing power consumption in a digital system. These methods and systems broadly provide for permitting clients executing on a digital system to register for notification of power event and to request that power events occur. Registered clients are notified when a power event is requested and the requested power event is caused to occur. Power events are selected from a group comprising setpoint change, enter deep sleep mode, enter snooze mode, and change to power supply status. There may also be user-defined custom power events. If the requested power event is a setpoint change, a check is made to verify that each of the registered clients can operate at the requested setpoint. The digital system may be comprised of processor with a single processing core with a single clock or a processor with multiple processing cores and multiple clocks.

Methodology for managing power consumption in an application

A system ( ) for interfacing hardware and software components in a simulation system is disclosed. The present invention includes at least one cell ( ) having a model access and control hub ( ) and at least one block ( ) within the cell ( ) connected to the model access and control hub ( ). The block ( ) executes a command ( ) sent by the model access and control hub ( ). The present invention also includes an interprocess communication device ( ) including shared memory ( ) coupled to the model access and control hub ( ). The shared memory ( ) communicates the command ( ) to the model access and control hub ( ). The present invention also includes a debugger ( ) coupled to the interprocess communication device ( ) that issues the command ( ) to the model access and control hub ( ) via the shared memory ( ), and receives information from the model access and control hub ( ) via the shared memory ( ). The present invention also includes an antenna ( ) coupled to the model access and control hub ( ) for communicating within the system ( ), and for receiving and transmitting information.

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Karnataka, India

Vijaya B P Sarathy