Fairchild Semiconductor Corporation

Maxim Integrated Products, Inc.

Vijay Ullal

Daniel Marvin Kinzer

Chung-Lin Wu

Oseob Jeon

Maria Cristina Estacio

Ahmad Ashrafzadeh

Justin N Chiang

Michael M Dube

Arkadii V Samoilov

Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Wafer-level package device

In one general aspect, a method can include forming a redistribution layer on a substrate using a first electroplating process, and forming a conductive pillar on the redistribution layer using a second electroplating process. The method can include coupling a semiconductor die to the redistribution layer, and can include forming a molding layer encapsulating at least a portion of the redistribution layer and at least a portion of the conductive pillar.

Package including a semiconductor die and a capacitive component

Apparatus related to an improved package including a semiconductor die

Growing community of inventors

Saratoga, CA, United States of America

Vijay Ullal