Cypress Semiconductor Corporation

Vijay Srinivasaraghavan

Ryan Tasuo Hirose

Fredrick B Jenne

Igor G Kouznetsov

Bogdan I Georgescu

Cristinel Zonte

Leonard Vasile Gitlan

Paul Fredrick Ruths

James Paul Myers

Stefan-Cristian Rezeanu

James D Allan

Eric Wolf Gross

Emad Hamadeh

Robert W Manning

In embodiments described herein, a memory architecture has an array of non-volatile memory cells and a pair of independently controlled voltage pumps. The pair of voltage pumps is coupled for supplying both positive and negative voltage biases to the memory array during program and erase operations, such that a sum of the magnitudes of the positive and negative voltage biases is applied across a storage node of an accessed memory cell.

Memory architecture having two independently controlled voltage pumps

A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to provide accurate sensing, a reference current generator is provided and coupled to the sense amplifier. The reference current generator provides a first reference current having adjustable magnitude and adjustable slope, and a second reference current having adjustable magnitude, but constant slope. The first reference current is supplied to the sense amplifier for sensing the data bit. The second reference current is supplied to a control block for generating clock signals used to control sense amplifier timing.

Memory architecture having a reference current generator that provides two reference currents

A circuit for discharging a high voltage signal to a supply voltage line. In one embodiment, the circuit includes a first switch receiving the high voltage signal; a second switch having an input coupled with the output of the first switch; and a third switch having an input coupled with the output of the second switch and having an output coupled with the supply voltage line. In this embodiment, the high voltage signal discharges to the supply voltage line when the first, second, and third switches are on. The circuit may include a fourth switch for clamping the high voltage signal to ground. The fourth switch may have a control coupled with the output of the first switch along a discharge path such that when the high voltage signal is discharging and approaches a voltage level of approximately ground, the fourth switch automatically turns on and clamps the high voltage signal to ground level. In this manner, after the high voltage signal has discharged, the fourth switch clamps the high voltage signal to a ground potential so that circuit elements coupled with the high voltage signal may operate.

Circuit and method for discharging high voltage signals

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports

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Colorado Springs, CO, United States of America

Vijay Srinivasaraghavan