Oracle International Corporation

Fortinet, Inc.

Vijay Srinivasan

Sebastian Turullols

Rajesh I Balay

Chandramouli Sargor

Changku Hwang

John Crawbuck

Sanjeev Tyagi

Pasula Srinivasa Reddy

Yifan YangGong

An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

Integrated circuit current metering using voltage variation detection circuit

Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.

High sensitivity digital voltage droop monitor for integrated circuits

Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.

Digital voltage droop monitor with clock jitter adjustment

Methods and Systems are provided for a distributed Provider Edge (PE). A single Virtual Routing and Forwarding device (VRF) is associated with a single customer site. The VRF includes a single routing table (RIB) and a single forwarding table (FIB). The VRF also includes a plurality of Virtual Private Network (VPN) Protocol Instance Modules (VRP), where each VRP is associated with a different VPN from the customer site. Each VRP accesses the RIB directly and the FIB indirectly to acquiring addressing/routing information for a received data packet. Moreover, each VRP uses a data plane of the VRP to communicate the data packets to a PE backbone device. In turn, the PE backbone device uses the data plane to communicate with each of the VRPs, and the PE backbone device communicates with one or more tunnels.

Growing community of inventors

Palo Alto, CA, United States of America

Vijay Srinivasan