Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Vijay Sivasankaran

Dinesh Kumar Agarwal

Abhijeet Manohar

Vimal Kumar Jain

Oleg Kragel

Vivek Shivhare

Chetan Agrawal

Xiangyu Tang

Amir Segev

Narendhiran Chinnaanangur Ravimohan

Ramkumar Ramamurthy

Muralitharan Jayaraman

Mikhail Palityka

Sourabh Sankule

Arun Thandapani

Nagi Reddy Chodem

Jonathan Journo

Krishnamurthy Dhakshinamurthy

Chaitanya Kavirayani

Nava Eisenstein

Rishabh Dubey

Sampath Raja Murthy

Kumar Amarjit

Satish Kumar

Anshul Modi

An indexless logical-to-physical translation table (L2PTT). In one example, the data storage device including a memory, a data storage controller, and a bus. The memory including a mapping unit staging page that includes a plurality of mapping unit pages and a mapping unit page directory. The data storage controller including a data storage controller memory and coupled to the memory, the data storage controller memory including an indexless logical-to-physical translation table (L2PTT). The bus for transferring data between the data storage controller and a host device in communication with the data storage controller. The data storage controller is configured to perform one or more memory operations with the indexless L2PTT.

Indexless logical-to-physical translation table

Aspects of a storage device are provided that allow a controller to leverage cache to minimize occurrence of HMB address overlaps between different HMB requests. The storage device may include a cache and a controller coupled to the cache. The controller may store in the cache, in response to a HMB read request, first data from a HMB at a first HMB address. The controller may also store in the cache, in response to an HMB write request, second data from the HMB at a second HMB address. The controller may refrain from processing subsequent HMB requests in response to an overlap of the first HMB address with an address range including the second HMB address, and the controller may resume processing the subsequent HMB requests after the first data is stored. As a result, turnaround time delays for HMB requests may be reduced and performance may be improved.

Host memory buffer (HMB) random cache access

Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.

Identification and classification of write stream priority

Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.

Method and apparatus for wear-levelling non-volatile memory

Aspects of the disclosure provide for managing a logical to physical (L2P) table in a Solid State Drive (SSD). Methods and apparatus provide for using a non-volatile memory (NVM) to store the L2P table in its entirety, where the L2P table is separated into a plurality of partitions. The SSD is partitioned into front and back-end processing portions where a partition table is managed by the back-end portion and includes one or more addresses of partitioned portions of the plurality partitions of the L2P table stored in the NVM. The back-end processing portion receives requests from the host via the front-end processing portion and accesses the partition table for scheduling read or write access to the NVM by determining one or more addresses of the respective partitioned portions of the plurality partitions of the L2P table stored in the NVM from the partition table.

Methods and apparatus for implementing a logical to physical address mapping in a solid state drive

A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types

In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.

Block management scheme to handle cluster failures in non-volatile memory

A memory system or flash card may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space may be organized with a large logical group size for sequential data. For fragmented data, the GAT may reference an additional GAT page or additional GAT chunk that has a smaller logical group size.

Dynamic logical groups for mapping flash memory

Method and apparatus for wear-leveling non-volatile memory

A storage module may be configured to organize data to be moved from an initial storage location to a destination storage location into sets, and to determine whether to commit the data to the destination storage location on a set-by-set basis. Error correction and/or a post write and read process may be performed on the sets that are copied to the destination storage location to determine whether to commit each of the copied sets.

Moving and committing valid data on a set-by-set basis

A solution for combining a portion of data from a block of single level cells to a block of multi-level cells. The solution includes identifying word lines with only valid data and word lines with non-valid data in a selected block of single level cells, copying data from word lines with valid data to a destination block of multi-level cells and copying data from word lines in the selected block of single level cells with non-valid data to a separate compaction block of single level cells. The system includes a first controller module configured to scan for word lines with only valid data and pass a bitmap identifying valid and invalid word lines to a second controller module. The second controller module is configured to perform on-chip combining of data from valid word lines, and copy data from invalid data word lines to a compaction block of single level cells.

System and method for folding partial blocks into multi-level cell memory blocks

A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information.

Initialization scheme during dual programming of a memory system

A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased.

Protection scheme with dual programming of a memory system

A system handles bad blocks in block-based NAND memory by remapping wordlines that are unusable. Rather than eliminate usage of an entire block, the system may dynamically remap the block to exclude only the unusable wordlines. The partial blocks utilize portions of the memory with good wordlines and the portions of memory with bad wordlines are redirected to one or more replacement blocks.

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Bengaluru, India

Vijay Sivasankaran