Synplicity, Inc.

Synopsys, Inc.

Cycuity, Inc.

Vijay Seshadri

Kenneth S McElvain

Jason K Oberg

Kristoffer Wilkerson

Alric Althoff

Nicole Fern

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for analyzing hardware designs for vulnerabilities to side-channel attacks. One of the methods includes receiving a request to analyze a device hardware design for side-channel vulnerabilities in the device after being manufactured. Physical characteristics data is obtained representing one or more physical characteristics of the device based on the device hardware design. Information flow analysis is performed to identify one or more signals of interest corresponding to digital assets. From the physical characteristics data and the one or more signals of interest, data representing potentially vulnerable signals in the device hardware design is generated. A leakage model is generated for the potentially vulnerable signals that quantifies one or more leakage criteria for one or more structures of the device hardware design.

Analyzing hardware designs for vulnerabilities to side-channel attacks

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for identifying security vulnerabilities introduced by transformations to a hardware design. One of the methods includes obtaining a security model for an initial electronic hardware design and a modified electronic hardware design. An analysis process is performed on the initial representation and on the modified representation of the electronic hardware design according to the security model. If the modified electronic hardware design introduced a security vulnerability relative to the initial electronic hardware design, information representing the introduced security vulnerability is provided.

Detecting security vulnerabilities introduced between versions of a hardware design

Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.

Methods and apparatuses for automated circuit optimization and verification

A resetable memory is described that includes a memory without reset capability having a data output coupled to a first input of a first multiplexer. A second input of the first multiplexer has a reset value input. A channel select for the first multiplexer is coupled to a resetable storage cell output that indicates whether a storage cell within the memory without reset capability has been written to after a reset or has not been written to after a reset.

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San Jose, CA, United States of America

Vijay Seshadri