Intel Corporation

Vijay S R Degalahal

Efraim Rotem

Eliezer Weissmann

Nadav Shulman

Tal Kuzi

Jawad Haj-Yihia

Ravishankar Iyer

Andrew J Herdrich

Avinash N Ananthakrishnan

Nir Rosenzweig

Itay Franko

Amit Gur

Robert E Gough

Ashish V Choubal

Rameshkumar G Illikkal

Karthi R Vadivelu

Chia-Hung Sophia Kuo

Jaideep Moses

Sadagopan Srinivasan

Pronay Dutta

Jared E Bendt

Panner Kumar

Alon Naveh

James G Hermerding Ii

Benjamin J Gould

Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

Autonomous C-state algorithm and computational engine alignment for improved processor power efficiency

In one embodiment, a system on chip includes: at least one core; a plurality of intellectual property (IP) agents coupled to the at least one core; a shared power rail to provide an operating voltage to the plurality of IP agents; and a power controller, in response to an indication that the plurality of IP agents are in an idle state and the at least one core is in an active state, to power down the shared power rail while the at least one core remains in the active state. Other embodiments are described and claimed.

System, apparatus and method for collective power control of multiple intellectual property agents and a shared power rail

Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.

Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing

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Bengaluru, India

Vijay S R Degalahal