Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Infineon Technologies LLC

Longitude Elash Memory Solutions Ltd

Vijay Raghavan

Cristinel Zonte

Bogdan I Georgescu

Iulian Constantin Gradinariu

Gary Peter Moscaluk

Roger J Bettman

Samuel Leshner

Vineet Argrawal

Igor G Kouznetsov

Ryan Tasuo Hirose

Fredrick B Jenne

Jayant Ashokkumar

Leonard Vasile Gitlan

Paul Fredrick Ruths

James Paul Myers

Hans Van Antwerpen

Sean B Mulholland

Ashish Ashok Amonkar

Bogdan Samson

Ramesh Chettuvetty

Venkatraman Prabhakar

Swatilekha Saha

Gary P Mosculak

In accordance with an embodiment, a method for characterizing a non-volatile memory, includes: applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current flowing through the non-volatile memory cell in response to applying the first voltage. Measuring the current includes: using a sense amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source while applying the same first voltage on the word line, and determining the measured current based on the comparing.

System and method for testing a non-volatile memory

A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.

In-memory computing architecture and methods for performing MAC operations

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Low standby power with fast turn on method for non-volatile memory devices

In-memory computing architectures and methods of performing multiply-and-accumulate operations are provided. The method includes sequentially shifting bits of first input bytes into each row in an array of memory cells arranged in rows and columns. Each memory cell is activated based on the bit to produce a bit-line current from each activated memory cell in a column on a shared bit-line proportional to a product of the bit and a weight stored therein. Charges produced by a sum of the bit-line currents in a column are accumulated in first charge-storage banks coupled to a shared bit-line in each of the columns. Concurrently, charges from second input bytes accumulated in second charge-storage banks previously coupled to the columns are sequentially converted into output bytes. The charge-storage banks are exchanged after the first input bytes have been accumulated and the charges from the second input bytes converted. The method then repeats.

A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

High voltage architecture for non-volatile memory

Low standby power with fast turn on for non-volatile memory devices

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Memory architecture having two independently controlled voltage pumps

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.

Biasing circuit for level shifter with isolation

A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Split voltage non-volatile latch cell

A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Growing community of inventors

Colorado Springs, CO, United States of America

Vijay Raghavan