Atmel Corporation

Vijay P Adusumilli

Nicola Telecco

Stephen Trinh

Anil Gupta

Steven J Schumann

Edward S Hui

Alan Chen

Neville B Ichhaporia

A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address interface that is used to send address, data, and commands between the controller device and the one or more memory devices. A method of transferring information between the controller device and the one or more non-volatile memory devices includes resetting the one or more non-volatile memory devices by asserting a high-voltage signal on the high-voltage reset interface and sending a command from the controller device to the one or more non-volatile memory devices via the data and address interface.

Off-chip micro control and interface in a multichip integrated memory system

A memory circuit and a method of operating a flash or EEPROM device that has two levels of internal cache. A memory device having a memory array, sense amplifiers, a data register, cache, an input-output circuit, and a control logic circuit is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.

High-speed interface for high-density flash with two levels of pipelined cache

Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.

Redundancy scheme in memory

A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.

Column redundancy RAM for dynamic bit replacement in FLASH memory

A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

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San Jose, CA, United States of America

Vijay P Adusumilli