International Business Machines Corporation

Globalfoundries Inc.

Ulvac, Inc.

Tokyo Electron Limited

The State University of New York

Centre National De La Recherche Scientifique

Vijay Narayanan

Takashi Ando

Vamsi Krishna Paruchuri

Martin Michael Frank

Eduard Albert Cartier

Unoh Kwon

Michael Patrick Chudzik

Hemanth Jagannathan

Ruqiang Bao

Bruce Bennett Doris

Supratik Guha

Siddarth A Krishnan

Paul Charles Jamison

Rajarao Jammy

Barry P Linder

Cyril Cabral, Jr

Kisik Choi

Renee Tong Mo

Matthew Warren Copel

Jeffrey W Sleight

Evgeni Petrovich Gousev

Choonghyun Lee

Sufi Zafar

Hiroyuki Miyazoe

Dae-Gyu Park

Fenton Read McFeely

Ravikumar Ramachandran

Pouya Hashemi

Ghavam G Shahidi

Josephine B Chang

Pranita Kerber

Huiming Bu

Dechao Guo

Keith Kwong Hon Wong

Xiao Lin Sun

Devendra K Sadana

Tenko Yamashita

Terence B Hook

Christian Lavoie

Herbert Lei Ho

Dirk Pfeiffer

Tze-Chiang Chen

Seyoung Kim

Deborah A Neumayer

Chung H Lam

Michael A Guillorn

Ying Di Zhang

Daniel Joseph Friedman

Arvind Kumar

Sanjay C Mehta

Ramachandran Muralidhar

Frank Robert Libsch

Robert L Wisnieff

Richard Harold Boivie

Brent A Anderson

Effendi Leobandung

Junli Wang

Carl John Radens

Clement Hsingjen Wann

Nicolas J Loubet

Yun Yu Wang

Kevin K Chan

Reinaldo Ariel Vega

Kern Rim

Leland Chang

Hiroaki Niimi

Zhengwen O Li

Koji Watanabe

Kandabara N Tapily

Yun-Yu Wang

Muthumanickam Sankarapandian

Emre Alptekin

Richard Alan Haight

Wesley Charles Natzle

Kathryn Turner Schonenberg

Chih-Chao Yang

Stephen W Bedell

Oleg Gluschenkov

Son Van Nguyen

Sivananda K Kanakasabapathy

Takeshi Nogami

Soon-Cheon Seo

Baozhen Li

Katherine Lynn Saenger

Praneet Adusumilli

Kenneth Parker Rodbell

Jack Oon Chu

Paul Michael Solomon

Stephen McConnell Gates

Richard Stephan Wise

Shreesh Narasimha

Teodor Krassimirov Todorov

Marwan H Khater

Nicholas Anthony Lanzillo

Robert Daniel Clark

Peilin Song

John Christopher Arnold

Kwong Hon Wong

James N Pan

Yumiko Kawano

A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

Self-aligned metal gate with poly silicide for vertical transport field-effect transistors

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

RRAM structures in the BEOL

Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Topological semi-metal interconnects

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing Hgas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Method for controlling the forming voltage in resistive random access memory devices

A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.

Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device

A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CHF)-based plasma chemistry or a fluorocarbon (CF)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.

Oxygen-free plasma etching for contact etching of resistive random access memory

Artificial synaptic devices with an HfO-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400&#xb0; C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS back-end

Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

Device with pure silicon oxide layer on silicon-germanium layer

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or AlC, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 &#x212b;. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

Conformal replacement gate electrode for short channel devices

A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.

A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.

Resistive switching memory with replacement metal electrode

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device

A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

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New York, NY, United States of America

Vijay Narayanan