Intel Corporation

Google Inc.

Vijay Menon

Tatiana Shpeisman

Ali-Reza Adl-Tabatabai

Bratin Saha

Peng Li

Richard Lewis Hudson

Leaf Petersen

Brian R Murphy

Ali-Reza Adl-Tabataba

A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.

Optimizing quiescence in a software transactional memory (STM) system

A method and apparatus for optimizing weak atomicity overhead is herein described. A state table is maintained either during static or dynamic compilation of code to track data non-transactionally accessed. Within execution of a transaction, such as at transactional memory accesses or within a commit function, it is determined if data associated with memory access within the transaction is to be conflictingly accessed outside the transaction from the state table. If the data is not accessed outside the transaction, then the transaction potentially commits without weak atomicity safety mechanisms, such as privatization. Furthermore, even if data is accessed outside the transaction, optimized safety mechanisms may be performed to ensure isolation between the potentially conflicting accesses, while eliding the mechanisms for data not accessed outside the transaction.

Optimization for safe elimination of weak atomicity overhead

A system, method and a computer-readable medium for processing resources on a multithreaded browser. The browser includes a main thread and receives a resource. The browser initializes the main thread, the main thread includes an event loop and initializes a plurality of virtual machines, one virtual machine for each code segment within the resource. Each virtual machine includes a UI thread and is configured to share the main thread within the browser with the UI thread. Each UI thread is further configured to execute an event scheduled on the event loop on the virtual machine.

Multi-threaded virtual machine processing on a web page

A method and apparatus for dynamic optimization of strong atomicity barriers is herein described. During runtime compilation, code including non-transactional memory accesses that are to conflict with transactional memory accesses is patched to insert transactional barriers at the conflicting non-transactional memory accesses to ensure isolation and strong atomicity. However, barriers are omitted or removed from non-transactional memory accesses that do not conflict with transactional memory accesses to reduce barrier execution overhead.

Dynamic optimization for removal of strong atomicity barriers

A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

Efficient non-transactional write barriers for strong atomicity

A method for managing a transaction includes determining that an optimistically immutable field in the transaction is written to. Invaliding a method in response to determining that the method in the transaction reads is the optimistically immutable field. Other embodiments are disclosed and claimed.

Method and apparatus for performing dynamic optimization for software transactional memory

A compiler can perform aggressive code motion optimization by respecting value dependence of safety values inserted into the intermediate representation of a computer program. In one embodiment, the present invention includes converting a computer program into an intermediate representation, the intermediate representation containing at least one safety check ensuring the safety of at least one dangerous instruction. In one embodiment, the invention further includes defining a safety value in the intermediate representation as the safety check and including the safety value as a safety argument of the dangerous instruction. In one embodiment, it is determined that the safety check is redundant. In response, in one embodiment, the invention includes updating the safety argument of the dangerous instruction, and eliminating the safety check from the intermediate representation during the safety check elimination optimization. Other embodiments are described and claimed.

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Seattle, WA, United States of America

Vijay Menon