National Semiconductor Corporation

Aptix Corporation

Vijay M Sajja

Siamak Jonaidi

Ranjan J Mathew

Jagdish G Belani

Yung-Shih Chen

Jagdish Belane

A method for fabricating a printed circuit board for high pin count surface mount pin grid arrays is provided where surface mount pads for soldering a surface mount pin grid array package are isolated by solder mask layers. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

Circuit board for high pin count surface mount pin grid arrays

A printed circuit board is provided with surface mount pads for soldering a surface mount pin grid array package. The printed circuit board is laminated with one or more solder mask layers containing apertures therein to expose the surface mount pad locations.

A method for solder plating metal leads in plastic semiconductor packages comprises cleaning the leads followed by electroplating tin or a tin/lead alloy onto the leads. The cleaning is effected with a non-corrosive solution which is either a carboxylic acid, a hydroxycarboxylic acid, or a combination of both. The electroplating solution is a sulfonic acid or citric acid based system, including suitable tin salts and/or lead salts. A sequestering agent may be used to inhibit the corrosive effect of the electroplating bath.

Solder plating process and semiconductor product

A solder composition of 10 to 40 percent tin, with the balance lead, for use in thin layers of 50 to 500 microinches on copper integrated circuit leads so as to resist the formation of intermetallics when later heated.

Growing community of inventors

Fremont, CA, United States of America

Vijay M Sajja