Apple Inc.

Apple Ine.

Vijay M Bettada

Bo Yang

Bibo Li

Dragos F Botea

Brijesh Tripathi

Michael R Seningen

Erik P Machnicki

Toshinari Takayanagi

Jung Wook Cho

Eric G Smith

Matthias Knoth

Antonietta Oliva

Kiran Kattel

Samy R Makar

Vasu P Ganti

Khaled M Alashmouny

Andrew J Copperhall

Anuja Banerjee

Wenlong Wei

An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

Scan chain analysis using predefined capture signature

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

Power droop measurements using analog-to-digital converter during testing

Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Memory testing system

A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

Hardware assisted scheme for testing memories using scan

An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Under voltage detection and performance throttling

A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Transition fault testing of source synchronous interface

Growing community of inventors

Fremont, CA, United States of America

Vijay M Bettada