Cypress Semiconductor Corporation

Vijay Kumar Srinivasa Raghavan

Iulian Constantin Gradinariu

Ryan Tasuo Hirose

Cristinel Zonte

Leonard Vasile Gitlan

Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Substrate bias feedback scheme to reduce chip leakage power

A method of biasing a circuit includes generating a control bias signal based on a difference between a leakage current of a baseline circuit and a reference signal; applying the control bias signal to a charge pump circuit to set a value of a reverse body bias voltage output from the charge pump, the control bias signal providing analog control of a digital clock of the charge pump circuit; and applying the reverse body bias voltage to a body of the baseline circuit.

A SONOS memory sensing scheme includes a reference current circuit that tracks the changes in the power supply (Vcc). An equalizer of the current sense amplifier is coupled between the read out current line and the reference current line. The current sense amplifier includes data and datab (data bar) outputs which have a common mode noise due to variations in the power supply voltage. The data output is a current generated from the memory cell, and the datab output is generated by the current reference circuit.

Power supply tracking single ended sensing scheme for SONOS memories

A device for providing a high precision current reference comprising a PTAT generator circuit for supplying a voltage, a high precision current reference offset generator circuit for generating a high precision current offset to compensate for variation in a resistance component due to variation in temperature, and a current adding circuit for aggregating the current from the PTAT generator circuit and the current from the high precision current reference offset generator circuit. In one embodiment, a high precision current reference generated is substantially independent of temperature. On-chip resistors may be used to design a high precision current reference. Accordingly, high precision current reference generated maintains high precision with zero temperature co-efficient using on-chip resistors that are substantially cheaper than off-chip resistors.

High precision current reference using offset PTAT correction

A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.

A method of optimizing memory cell write/read is disclosed. The memory cell write/read is optimized by first reading the memory cell data using the normal mode. Next the page latch data that was used to NV (Non-Volatile) write the memory is also read back directly from the page latches. The two data are then compared to verify a successful and optimized memory cell write/read. NV writes and reads are performed with various high voltage parameters and sense amplifier reference settings to arrive at the most optimal one that gives the largest sense window for best write/read reliability. The page latch read mode is also used as a DFT (Design for Test) test mode to check for page latch functionality and page address uniqueness without having to write the memory cell. The page latch is written with logic data and read out directly using the page latch read mode to verify page functionality.

Memory test and setup method

A relatively precise and accurate current reference system and method are described. The present current reference system and method facilitate realization of relatively high accuracy and precision in current references independent of process, voltage and temperature (PVT) variations. In one embodiment, a current reference system includes an opamp (operational amplifier), a first transistor and second transistor, a first resistor and a second resistor of different temperature coefficients, and a third transistor and fourth transistor. The opamp indicates and corrects the potential difference between a first branch and a second branch. The first transistor and second transistor mirror currents in the first branch and the second branch. The first resistor and a second resistor of different temperature coefficients cause voltage drops across them in a manner that compensates for PTAT variations. The third transistor and fourth transistor provide voltages between respective bases and emitters.

Current reference system and method

A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential at a load control node. A reference current circuit can be coupled between the first load device and a second power supply node that includes a current reference section that provides an impedance according to a bias voltage. A data current circuit can be coupled between the second load device and a plurality of memory cells. An adaptive bias circuit can be coupled between the first power supply and the second power supply node and can include a bias section coupled to the load control node that provides an impedance according to the bias voltage.

Adaptive current sense amplifier with direct array access capability

The invention has a bootstrapped high voltage pass gate transistor that couples the low voltage sense amplifier to the bitlines. Since the pass gate transistor is bootstrapped its gate floats to the high voltage of the power supply (VCC) plus a delta voltage. This overdrives the pass gate transistor and allows it to pass signals between the sense amplifier and the bitlines with low impedance. This results in good sense differential margins and fast read speeds. The circuit has a pass gate control circuit that places a negative high voltage signal on the gate of the pass gate during non-volatile write operations. This causes the pass gate to isolate the low voltage circuit from the high voltage circuits during this operation. Finally, the circuit is smaller than earlier column multiplexer circuits.

Low impedance column multiplexer circuit and method

System and methods to adjust a reference current are disclosed. A current reference circuit generates an adjustable reference current. A microprocessor-based feedback circuit adjusts the reference current, wherein the adjustment is based on read and write parameters attributed to a memory cell.

System to adjust a reference current

A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.

High speed circuit and a method to test memory address uniqueness

Disclosed are a circuit and a method for a high speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation. The circuit includes a low voltage driver. A gate bootstrapped transistor is coupled to the low voltage driver. A first transistor is coupled to an output terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal. A second transistor is coupled to a gate terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal.

High speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation

Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.

Growing community of inventors

Colorado Springs, CO, United States of America

Vijay Kumar Srinivasa Raghavan