Texas Instruments Corporation

Vijay Kumar Reddy

Srikanth Krishnan

Anand T Krishnan

Gianluca Boselli

Min Chen

Andrew Marshall

John Anthony Rodriguez

Ekanayake Ajith Amerasekera

Cathy A Chancellor

Srinath Mathur Ramaswamy

Brian Paul Ginsburg

Chih-Ming Hung

Siraj Akhtar

Jeremy Charles Smith

Robert L Pitts

Kamel Benaissa

Timothy Alan Rost

John Michael Carulli, Jr

Karan Singh Bhatia

Samuel Edward Martin

Prasun K Raha

Paul Edward Nicollian

Gautam Kapila

T Krishnaswamy

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

Devices under test

An integrated circuit includes a circuit aging sensor that provides information regarding operational degradation of the integrated circuit due to aging. The aging sensor includes a ring oscillator that includes inverting drivers and tuning circuits. The drivers are sequentially coupled to form a ring. An output of each of the drivers is coupled to an input of one of the tuning circuits, and an input of each of the drivers is coupled to an output of one of the tuning circuits. Each of the tuning circuits includes a first signal path and a second signal path. The first signal path selectably applies a tuning delay to an input signal received from one of the drivers for provision to an input of a successive one of the drivers. The second signal path selectably routes the signal received around the tuning delay to the input of the successive one of the drivers.

Circuit aging sensor

A method includes, for a device and at each of a plurality of sampling frequencies, measuring a parameter of the device to generate a plurality of signals and each signal represents a time series of values of the parameter. Further, the method includes for each of the plurality of signals, identifying at least two stable states in the time series for each signal. Still further, the method includes determining a time constant associated with each stable state of each signal, determining a relationship between the time constants of each stable state and sampling frequency, and computing a final time constant value for each steady state by computing a derivative of the time constants as a function of sampling frequency relationship and comparing the derivative to a threshold.

Methods and systems to determine a final value of random telegraph noise time constant and magnitude

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

Variability and aging sensor for integrated circuits

An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.

High performance asymmetric cascoded transistor

A set of parameter drifts is recorded over a period of time for each of a series of stress tests on a system at various stress levels. Each set of the recorded parameter drifts is plotted as parameter drift versus time. The plots are then time shifted in relation to a reference plot to form a single parameter drift plot. A non-linear equation is fitted to the single parameter drift plot and then used to predict parameter drift over the life of the system. The non-linear equation may be modified by adding a stress acceleration factor to allow prediction of parameter drift over time at different stress levels.

Parameter drift prediction

Various apparatuses and methods for varying segment activation in a segmented power amplifier are disclosed herein. For example, some embodiments provide a power amplifier including an input, an output, a plurality of amplifier segments and a controller. The amplifier segments are connected in parallel between the input and the output and are adapted to be activated and inactivated. The power level at the output may be controlled by changing a number of the amplifier segments that are activated concurrently. The controller is connected to the amplifier segments and is adapted to vary which of the amplifier segments are activated to arrive at a selected number of activated amplifier segments.

Segmented power amplifier with varying segment activation

One embodiment relates to an on-chip power amplifier (PA) test circuit. In one embodiment, a PA test circuit comprises a controllable oscillator (CO) configured to generate a radio frequency (RF) signal, a parallel resonant circuit tuned to the radio frequency, a pre-power amplifier (PPA) coupled to the CO and the parallel resonant circuit, the PPA configured to amplify and drive the RF signal from an output of the PPA into a load. The test circuit may further comprise a first transmission gate configured to couple the RF signal from the CO to an input of the PPA. One testing methodology for a PA test circuit comprises stressing the PPA with an RF signal, measuring a characteristic of the PPA, determining stress degradation from the characteristic measurements, and repeating the stressing and characteristic measurements until a maximum stress degradation is achieved or a maximum stress has been applied.

Methodology for assessing degradation due to radio frequency excitation of transistors

Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.

Tunable stress technique for reliability degradation measurement

A method for evaluating gate dielectrics () includes providing a test structure (). The test structure includes a gate stack that includes a gate electrode on a gate dielectric on a substrate, and at least one diffusion region diffused in the substrate including a portion below the gate stack and a portion beyond the gate stack. Pre-stress off-state I-V testing () is performed on the test structure to obtain pre-stress I-V test data, wherein the pre-stress off-state I-V testing includes a first measurement involving the gate electrode, the substrate and the diffusion region, a second measurement involving the gate electrode and the substrate with the diffusion region floating, and a third measurement involving the gate electrode and the diffusion region with the substrate floating. The test structure is then stressed () including electrically stressing for a time (t). Following the stressing, post-stress I-V testing is performed () wherein the first, second and third measurements are repeated to obtain post-stress I-V test data. The gate dielectric is evaluated () from the pre-stress and post-stress I-V test data.

Current-voltage-based method for evaluating thin dielectrics based on interface traps

Methods and systems are provided for determining efficacy of stress protection circuitry. The methods and systems employ a ring oscillator that models at least one parameter of a functional circuit to be protected by the stress protection circuit. A stress signal is applied to the ring oscillator and parametric degradation is measured to determine the effectiveness of the stress protection circuit in protecting the ring oscillator. A stress signal can be a voltage or current that stresses the normal operation of a functional circuit. The parametric degradation of the ring oscillator can be correlated to the parametric degradation that would be experienced by the functional circuit.

Methods and systems for determining efficacy of stress protection circuitry

Apparatus are provided for fatigue testing ferroelectric material in a wafer, including an on-chip oscillator to provide a bipolar waveform to a ferroelectric capacitor formed in the wafer, as well as a switching system to selectively provide external access to the ferroelectric capacitor. Test methods are also disclosed provided, including measuring a performance characteristic of a ferroelectric capacitor in the wafer, providing a bipolar waveform to the ferroelectric capacitor for a number of cycles using an on-chip oscillator, and again measuring the performance characteristic after an integer number of cycles of the bipolar waveform.

Apparatus and methods for ferroelectric ram fatigue testing

Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

System and method for accurate negative bias temperature instability characterization

A PMOS ESD protection device is disclosed in which gate and substrate coupling techniques are implemented to afford protection during positive ESD events. A snapback leg in curves capable of being produced in accordance with one or more aspects of the present invention is removed, and a trigger voltage at which the device turns on is thereby reduced so as to be less than a second voltage corresponding to a second breakdown region.

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Plano, TX, United States of America

Vijay Kumar Reddy