Intel Corporation

Vijay Kumar Goru

Muthurajan Jayakumar

George Thangadurai

Richard W Goe

Ravi Eakambaram

An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Apparatus and method for initiating hardware priority management by software controlled register access

A system and method is provided for processing interrupt requests. The method is accomplished by detecting when an interrupt request is being stored in a storage location, examining the storage location storing the interrupt request, prioritizing the interrupt request when more than one interrupt request is stored in the storage location to determine an interrupt request processing order, clearing the interrupt request in the storage location that is to be processed, and processing the interrupt request. The system comprises a first storage location for storing an interrupt request, a second storage location for storing an interrupt handler program with encoded statements for examining the first storage location, prioritizing the interrupt request that is to be processed if more than one interrupt request is stored in said first storage location, clearing the interrupt request that is to be processed, and processing the interrupt request. The system further comprises a processor for executing the interrupt handler program.

Method and apparatus for processing more than one interrupts without

Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a particular interrupt input; if it does, determining whether that particular interrupt input is programmed to be a level-triggered interrupt; if it is, determining whether the level-status of that particular interrupt input is active; and, if it is, sending a level-triggered active message for the highest priority pending interrupt, by maintaining the set status of a particular bit. One embodiment of the present invention includes an interrupt service register operable to indicate when an interrupt is being serviced, an interrupt request register operable to indicate when an interrupt is pending, and a comparator operable to compare the vector corresponding to the highest priority pending interrupt with the vector associated with the particular interrupt input. Included also is a control generator coupled to the comparator, and operable to selectively clear and/or set bits contained in the interrupt service register and in the interrupt request register. The present invention supports both edge-triggered and level-triggered interrupts, without the need for a trigger mode register or other similar overhead house-keeping controls and related storage logic, and without any hand-shake requirements.

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San Jose, CA, United States of America

Vijay Kumar Goru