Virident Systems, Inc.

Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Viridient Systems, Inc

Sandisk Technologies Inc.

Vijay Karamcheti

Kenneth Alan Okin

Kumar Ganapathy

Ashish Singhai

Rajesh Parekh

Ashwin Narasimha

Shibabrata Mondal

Ajith Kumar

Swamy Gowda

George Moussa

Ruban Kanapathippillai

Krishanth Skandakumaran

Ladislav Steffko

Tanay Goel

Ankur Arora

Ajit Yagaty

Rajendra Prasad Mishra

William Henry Radke

Rodney Norman Mullendore

Bernd Lamberts

Sandeep Sharma

Ajith Kumar Battaje

Pinchas Herman

Saurabh Manchanda

Muthugopalkrishnan Adiseshan

Viswesh Sankaran

Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone.

Systems and methods for allocating blocks of memory to multiple zones associated with corresponding error correction mechanisms

By way of example, a data storage system may comprise, a non-transitory storage device storing data blocks in chunks, and a storage logic coupled to the non-transitory storage device that manages storage of data on the storage device. The storage logic is executable to receive a data stream for storage in a non-transitory storage device, the data stream including one or more data blocks, analyze the data stream to determine a domain, retrieve a pre-configured reference set based on the domain, and deduplicate the one or more data blocks of the data stream using the pre-configured reference set.

Reference set construction for data deduplication

Embodiments of the present invention provide systems and methods for recovering a high availability storage system. The storage system includes a first layer and a second layer, each layer including a controller board, a router board, and storage elements. When a component of a layer fails, the storage system continues to function in the presence of a single failure of any component, up to two storage element failures in either layer, or a single power supply failure. While a component is down, the storage system will run in a degraded mode. The passive zone is not serving input/output requests, but is continuously updating its state in dynamic random access memory to enable failover within a short period of time using the layer that is fully operational. When the issue with the failed zone is corrected, a failback procedure brings the system back to a normal operating state.

High availability state machine and recovery

Systems and methods for multi-zone data tiering for endurance extension in solid state drives

A data storage system comprises, a storage device having segments that are configured to store data, and storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker. A garbage collection (GC) barrier may be set based on serial numbers associated with backup segments, and the garbage collection barrier may be incrementally released by releasing the garbage collection barrier for each segment after the segment has been backed up. The storage logic may also record the deletion of a storage unit from the storage device in a deletion table, and retire deleted storage mappings in the deletion table responsive to generating the backup.

Indirection-based storage system backups using markers including sets of serial numbers associated with segments

The disclosed multi-device platform includes, by way of example, a system that receives a host command including a logical address and determines a hybrid storage device unit based on the logical address. The hybrid storage device unit has a set of hybrid physical storage devices and the set of hybrid physical storage devices includes one or more magnetic storage devices and one or more flash storage devices. The system selects a first plurality of physical storage devices from the set of hybrid physical storage devices, generates a plurality of device commands for the first plurality of physical storage devices based on the host command, and executes the plurality of device commands on the first plurality of physical storage devices.

Unified indirection in a multi-device hybrid storage unit

A system comprising a processor and a memory storing instructions that, when executed, cause the system to determine a first value of a first checkpoint associated with a first snapshot, receive a second value of a second checkpoint associated with a translation table entry from an additional source, determine whether the second value of the second checkpoint is after the first value of the first checkpoint, in response to determining that the second value of the second checkpoint is after the first value of the first checkpoint, retrieve the translation table entry associated with the second checkpoint from the additional source, and reconstruct the translation table using the translation table entry associated with the second checkpoint.

Checkpoint based technique for bootstrapping forward map under constrained memory for flash devices

A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains; responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment; allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains; storing the number of data grains and the redundancy data to the memory segment of the grain memory; determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied; and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.

Efficient cross device redundancy implementation on high performance direct attached non-volatile storage with data reduction

An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Network computer systems with power management

An apparatus for inline compression and deduplication includes a memory unit and a processor coupled to the memory unit. The processor is configured to receive a subset of data from a data stream and select a reference data block corresponding to the subset of data, in which the reference data block is stored in a memory buffer resident in the memory unit. The processor is also configured to compare a first hash value computed for the subset of data to a second hash value computed for the reference data block, in which the first hash value and the second hash value are stored in separate hash tables and generate a compressed representation of the subset of data by modifying header data corresponding to the subset of data responsive to a detected match between the first hash value and the second hash value in one of the separate hash tables.

Apparatus and method for inline compression and deduplication

Embodiments of the present invention include a memory unit and a processor coupled to a memory unit. The processor is operable to group a plurality of subsets of data from an input data stream and compute a first hash value corresponding to a first grouped subset of data. Additionally, the processor is operable to detect a match between the first hash value and a second hash value stored in a hash table. Furthermore, the processor is also configured to monitor a hash value match frequency for the input data stream in which the processor is operable to increment a counter value responsive to a detection of the match and determine an entropy level for the input data stream based on the counter value relative to a frequent hash value match threshold. The processor can generate an instruction to either initialize performance of a data compression operation when the counter value meets or exceeds the frequent hash value match threshold or refrain from the performance of the data compression operation when the counter value fails to meet the frequent hash value match threshold.

Apparatus and method for single pass entropy detection on data transfer

A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.

Growing community of inventors

Los Altos, CA, United States of America

Vijay Karamcheti