Nexabit Networks LLC

Tilera Corporation

Mellanox Technologies, Ltd.

Vijay K Aggarwal

Kenneth M Steele

Mathew Hostetter

Zbigniew Opalka

Christopher Firth

Thomas Kong

Henry Charles Benz

Christopher R Young

Carl Costantino

Gilbert R Miller

Himanshu C Shah

Processing packets in a system that includes a plurality of interconnected processing cores is described. The processing includes receiving packets into one or more queues, associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate, mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set, and processing the packets in the mapped processor cores according to the hierarchy.

Packet processing in a parallel processing environment

A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.

Pattern matching

Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

In Internet and related networks, a method of and system for substitute use of the normal checksum field space in information processing (IP) datagram headers for obviating current processing time and addressing space limitations, involving replacing the current checksum usage in the checksum field with its attendant processing time with further source host and destination host addresses of lesser processing time, thereby increasing the address space for the network and decreasing the require header processing time, and/or providing space for autonomous system numbers, a higher layer protocol-based routing information (including of the MPLS type) or for Virtual Private Networks Indentifiers in the header.

Internet and related networks, a method of and system for substitute use of checksum field space in information processing datagram headers for obviating processing speed and addressing space limitations and providing other features

A technique and system for manipulating, converting or adapting datagram headers as required during traverse from one interface of a networking device to another, by novel clocked micro-sequencing and selection amongst input and output FIFO data streams, through dividing input serial data streams into small groups of FIFO input data streams and feeding the groups parallely into a matrix of a multilane highway of header unit input data, constant data pattern and computational unit busses controlled by such micro-sequencing so as to enable such processing of packet datagram headers and the like at very high wire speed, but using low clock speeds, and in a scalable manner.

Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA)

A novel networking architecture and technique for transmitting both cells and packets or frames across a common switch fabric, effected, at least in part, by utilizing a common set of algorithms for the forwarding engine (the ingress side) and a common set of algorithms for the QoS management (the egress part) that are provided for each I/O module to process packet/cell information without impacting the correct operation of ATM switching and without transforming packets into cells for transfer across the switch fabric.

System architecture for and method of processing packets and/or cells in a common switch

A technique for encoding (and decoding) escape and other characters in data packets at high rates of speed in HDLC and similar data processing through the use of groups of FIFO data streams parallely fed to and from a multilane highway matrix of input data and escape character switched busses and at relatively low clocking speeds, while running multiple byte streams at a time.

Method of and apparatus for inserting and/or deleting escape characters into and from data packets and datagrams therefor on high speed data stream networking lines

Growing community of inventors

Marlboro, MA, United States of America

Vijay K Aggarwal