Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Vijay Chinchole

Yan Li

Sonam Agarwal

Pavithra Devaraj

Nitin Kumar Gupta

Amit Kumar Sharma

Toru Miwa

Tz-Yi Liu

Po-Shen Lai

Shiv Harit Mathur

Abhinandan Venugopal

Vinayak Ashok Ghatawade

Ramakrishnan Subramanian

Hiroyuki Mizukoshi

Henry Zhang

Yibo Yin

Jayesh Pakhale

Nisha Padattil Kuliyampattil

Harihara Sravan Ancha

Spyridon Georgakis

Akash Agarwal

Jay Patel

Naman Rastogi

Siva Raghu Ram Voleti

The disclosure provides data storage devices, methods, and apparatuses including, among other things, a NAND feature through which software may define logical die groups. Moreover, these logical die groups are indexed and operated with indexed single commands, which is selective-multi-casting to specific dies. In one implementation, a data storage device includes a NAND memory and a controller. The NAND memory including a plurality of dies. The controller is coupled to the NAND memory and configured to generate an index by assigning each die of the plurality of dies to one logical group of a plurality of logical groups, and create the plurality of logical groups in the NAND memory by sending one or more command sequences to the NAND memory that groups the plurality of dies into the plurality of logical groups based on the index that is generated.

Overhead reduction in data transfer protocol for data storage devices

A memory circuit included in a computer system includes a memory array that stores multiple program instructions included in compressed program code. In response to receiving a fetch instruction from a processor circuit, the memory circuit may retrieve a particular instruction from the memory array. The memory circuit may, in response to a determination that the particular instruction is a particular type of instruction, retrieve additional program instructions from the memory array using an address included in the particular instruction, and send the particular program instruction and the additional program instructions to the processor circuit.

Memory circuit for halting a program counter while fetching an instruction sequence from memory

A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

Dynamic re-evaluation of parameters for non-volatile memory using microcontroller

A data storage system includes a memory including a plurality of memory cells; and control logic configured to receive a first data string and determine a data type of the first data string. If the first data string is a combination command, the control logic obtains a plurality of sub-commands based on the first data string. Meanwhile, the control logic receives a second data string, determines that it represents an address, and decodes the address. While decoding the address or otherwise processing the second data string, the control logic performs a system operation specified by one of the sub-commands. The control logic also performs a memory operation, specified by another of the sub-commands, on one or more of the plurality of memory cells in accordance with the decoded address.

Command interface and pre-fetch architecture

Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.

Column redundancy data architecture for yield improvement

A method for reducing firmware size and increasing firmware performance. Core timing control conditions used by a die controller are converted into production ready core timing control conditions, from which firmware instructions are then generated. The production ready core timing control conditions comprise a plurality of fixed core timing control conditions. The firmware instructions are modified to determine core timing control condition values for fixed core timing control conditions before implementing storage operations, to store the core timing control condition values in global condition registers, and to modify references to fixed core timing control conditions to access the values in those global condition registers. Finally, the modified firmware instructions are stored on the die controller, which comprises a microcontroller configured to execute them.

Reducing firmware size and increasing firmware performance

An illustrative embodiment disclosed is a circuit including an edge-triggered flip-flop having a first input port, a first clock port, and a first output port. The edge-triggered flip-flop receives, at the first clock port, a strobe having a first edge and a second edge. The edge-triggered flip-flop receives, at the first input port, a control byte time-aligned with the first edge and a data byte time-aligned with the second edge. The edge-triggered flip-flop passes, to the first output port, the control byte based on the first edge and the data byte based on the second edge. The circuit includes an inputs/outputs (I/O) decoder coupled to the first output port. The I/O decoder sends the control byte to microcontroller and sends the data byte to memory cells.

System and method for a reconfigurable controller bridge chip

Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

Multicore on-die memory microcontroller

Growing community of inventors

Bengaluru, India

Vijay Chinchole