Freescale Semiconductor,inc.

Vijay Bhargava

Ashish Mathur

Kushagra Khorwal

Naveen Kumar

A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

Configurable cell design using capacitive coupling for enhanced timing closure

A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

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Gurgaon, India

Vijay Bhargava