Taiwan Semiconductor Manufacturing Comp. Ltd.

Headway Technologies, Incorporated

Vignesh Sundar

Yu-Jen Wang

Sahil Patel

Ru-Ying Tong

Dongna Shen

Guenole Jan

Huanlong Liu

Yi Yang

Jodi Mari Iwata

Luc Thomas

Jian Zhu

Tom Zhong

Jesmin Haq

Zhongjian Teng

Yuan-Jen Lee

Vinh Lam

Po-Kang Wang

Hideaki Fukuzawa

Santiago Serrano Guisan

A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MON, TIN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

Multilayer structure for reducing film roughness in magnetic devices

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Etching and encapsulation scheme for magnetic tunnel junction fabrication

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

MTJ device performance by adding stress modulation layer to MTJ device structure

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a NO:silane flow rate ratio of at least 1:1 but less than 15:1. A NO plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL/capping layer configuration wherein a first tunnel barrier (TB) has a substantially lower resistance x area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PLand PL, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RAis formed on PLto provide higher PLstability. The condition RA<RAand RA<RAis achieved when TBand the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Dual magnetic tunnel junction (DMTJ) stack design

A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FeCoBwherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/□m, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FeCoB)Mwhere w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

A fabrication process for an STT MTJ MRAM device includes steps of cooling the device at individual or at multiple stages in its fabrication. The cooling process, which may be equally well applied during the fabrication of other multi-layered devices, is demonstrated to produce an operational device that is more resistant to adverse thermal effects during operation that would normally cause a similar device not so fabricated to lose stored data and otherwise fail to operate properly.

Cooling for PMA (perpendicular magnetic anisotropy) enhancement of STT-MRAM (spin-torque transfer-magnetic random access memory) devices

A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Post treatment to reduce shunting devices for physical etching process

A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.

Nitride capping layer for spin torque transfer (STT) magnetoresistive random access memory (MRAM)

MTJ device performance by adding stress modulation layer to mtj device structure

A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H, or a reducing species.

Low resistance MgO capping layer for perpendicularly magnetized magnetic tunnel junctions

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance&#xd7;area (RA) product than RAfor an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1&#x3c;RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.

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Sunnyvale, CA, United States of America

Vignesh Sundar