Applied Micro Circuits Corporation

Viet Linh Do

Simon Pang

Mehmet Mustafa Eker

Hongming An

Wei Fu

Michael Hellmer

Arash Farhoodfar

Philip Michael Clovis

Sushil Kumar Singh

Kenneth Yun

Kirk Alvin Miller

Kevin Warren James

Jim Lew

Jianfeng Shi

George Bendak

David Thomas Dougherty

John Calvin Leung

A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Transmitters and receivers using a jitter-attenuated clock derived from a gapped clock reference

A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)&#x2212;(D&#x2212;N)/D), and where N/D&#x3c;1. An accumulator creates a sum of (D&#x2212;N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a k-bit quotient. The k-bit quotient is subtracted from (I+1) to generate a divisor.

Frequency synthesis with low resolution rational division

A system and method are provided for generating a jitter-attenuated clock using an asynchronous gapped clock source. The method accepts a first reference clock having a first frequency. Using the first reference clock, an asynchronous gapped clock is generated having an average second frequency less than the first frequency. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock. Then, DN and DD are averaged. In response to the averaging, an averaged numerator (AN) and an averaged denominator (AD) are generated. Finally, the first frequency (first reference clock) is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency.

Jitter-attenuated clock using a gapped clock reference

A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (f), where 1&#x2266;i&#x2266;k, associated with a corresponding plurality of synthesized frequency values (f). For each synthesized frequency value, a raw ratio of integers Npand Dpis calculated, such that:  A greatest common divisor (GCD) of Npand Dpand a primitive ratio of integers is found for each raw ratio of integers, such that:  Using the common clock frequency value (f), each primitive ratio of integers, each reference frequency value, and each GCD, a final ratio of integers Nand D, is calculated for each synthesized frequency value, where C is an integer value.

Frequency generation using a single reference clock and a primitive ratio of integers

A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.

Single clock cycle first order limited accumulator for supplying weighted corrections

A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=I(N/D)=I+N/D=(I+1)&#x2212;(D&#x2212;N)/D, and where N/D&#x3c;1 and Nand Dare integers. Nis reduced; N=I(N/D)=I+N/D=(I+1)&#x2212;(D&#x2212;N)/D, where I, N, and Dare integers, and N/D&#x3c;1. I, N, and Dare used to create a final numerator divisor. Dis reduced; D=I(N/D)=I+N/D=(I+1)&#x2212;(D&#x2212;N)/D, where I, N, and Dare integers, and N/D&#x3c;1. I, N, and Dare used to create a final denominator divisor. Finally, I, the final numerator divisor, and the final denominator divisor are used to create a final divisor.

Frequency synthesis with low resolution rational division decomposition

A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q&#x3c;1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Frequency synthesis rational division

A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.

Frequency reacquisition in a clock and data recovery device

Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal first synthesizer and reference signal frequencies, an out-of-lock condition is asserted and a VCO is reselected from the plurality of n VCOs. A mid-point control voltage is supplied to a control voltage input of the reselected VCO. A difference is measured between a mid-point synthesized signal frequency and the reference signal frequency. If the difference is less than a first threshold, the reselected VCO is assigned to generate the first synthesized signal frequency.

Adaptive phase-locked loop (PLL) multi-band calibration

A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2.

Flexible accumulator for rational division

An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase.

Clock and data recovery loop with ISI pattern-weighted early-late phase detection

An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. An I clock and a function-controlled oscillation cycle phase delay Q clock are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with the function-controlled varied phase delay Q clock, creating digital I-bit and varied phase delay Q-bit values, respectively. The values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing varied phase delay Q-bit values with I-bit values. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signals are generated.

ISI pattern-weighted early-late phase detector with function-controlled oscillation jitter tracking

An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing Q-bit values sampled by the varied delay Q clock. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signal are generated.

ISI pattern-weighted early-late phase detector with jitter correction

A system and method are provided for matching a signal (compClk) to a particular frequency band in a multiband communications device. The method accepts a compClk signal, a frequency source is selected from sources collectively covering a range of frequency bands, and a reference clock is supplied from the selected source. If the frequency of the compClk is greater than the reference clock frequency, a high frequency window sampler supplies a first frequency pattern detector output signal (fpdOut). Simultaneously, a low frequency window sampler compares the compClk signal with the reference clock. If the frequency of the compClk is less than the reference clock frequency, the low frequency window sampler supplies a second frequency pattern detector output signal (fpdOut). The selected frequency source is compared to fpdOutand fpdOutsignals, and a determination is made as to whether the selected frequency source coarsely matches the compClk frequency.

Frequency crossing detection using opposing pattern detectors

A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

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Viet Linh Do